Contact in planar NROM technology

• US 20060208281A1
• Filed: 03/13/2006
• Published: 09/21/2006
• Est. Priority Date: 03/17/2005
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Shappir, Assaf
• Granted Patent: US 8,053,812 B2
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating material previously deposited over the bit lines, and depositing contact material, wherein the second insulating material blocks effusion of the contact material beyond the contact holes. The distance between neighboring bit lines in the array does not include a margin for contact misalignment.

Claims

1. A method for fabricating a non-volatile memory array, the method comprising:

placing contacts over bit lines in a self-aligned manner.

2. The method according to claim 1 and wherein said placing comprises:

forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating material previously deposited over said bit lines; and

depositing contact material, wherein said second insulating material blocks effusion of said contact material beyond said contact holes.

3. The method according to claim 2 and wherein said forming comprises:

having column-like formations of a first insulating material previously deposited over said bit lines;

placing at least a layer of a second insulating material resistant to the removal of said first insulating material in spaces between said formations at least along exposed side surfaces of said first insulating material; and

removing said first insulating material to expose at least a portion of each of said bit lines.

4. The method according to claim 3 and wherein said placing comprises filling spaces between said formations with said second insulating material.

5. The method according to claim 3 and wherein said removing employs a removing substance to which said second insulating material is resistant.

6. The method according to claim 5 and wherein said removing substance is an etchant.

7. The method according to claim 4 and wherein said filling comprises:

depositing said second insulating material over said array at least in a contact area; and

etching said second insulating material to a level below the top of said formations.

8. The method according to claim 2 and wherein said first insulating material is oxide.

9. The method according to claim 2 and wherein said second insulating material is one of the following materials:

nitride and oxy-nitride.

10. The method according to claim 3 and wherein said removing is performed by etching until a level of said bit lines.

11. The method according to claim 2 and wherein said forming comprises:

having column-like formations of a first insulating material previously deposited over said bit lines;

depositing a liner of said second insulating material across said formations and the spaces between said formations;

filling gaps in said liner with HV CMOS spacers;

removing said liner to form wedge-topped spacers abutting said formations on each side;

depositing an insulator fill; and

removing said formations and said insulator fill above said formations until a level of said bit lines.

12. The method according to claim 11 wherein said first removing employs a removing substance to which said first insulating material is resistant.

13. The method according to claim 12 wherein said removing substance is an etchant.

14. The method according to claim 11 and wherein said first insulating material is oxide.

15. The method according to claim 11 and wherein said second insulating material is one of the following materials:

nitride and oxy-nitride.

16. The method according to claim 11 and wherein said insulator fill is at least one of said first insulating material and an insulating material having similar etching properties to said first insulating material.

17. An NVM array comprising:

a plurality of bit lines; and

a multiplicity of contacts each connecting one metal line to one of said bit lines,

wherein a distance between neighboring said bit lines does not include a margin for contact misalignment.

18. An NVM array comprising:

a plurality of bit lines;

a plurality of word lines crossing said bit lines, wherein said word lines are grouped into word line areas and wherein segments of said bit lines located in said word line areas are covered with insulator formations;

contact areas between neighboring said word line areas; and

contacts on said bit lines in said contact areas aligned with said formations in said word line areas.