Class D amplifier

• US 20060208794A1
• Filed: 03/15/2006
• Published: 09/21/2006
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Morishima, Morito
• Granted Patent: US 7,538,607 B2
• Time in Patent Office: Days
• US Class Current: 330/10
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers

Abstract

The invention is directed to a class D amplifier. According to the class D amplifier, sound data applied to an input terminal is supplied through a compensation circuit to a PWM circuit, from which a PWM signal is output. The PWM signal is converted to an analog signal through a first low pass filter, which is delivered to a speaker. On the other hand, the sound data is delayed by a delay circuit, and is converted to an analog signal by a digital to analog converter. The higher frequency components of the data are removed by a second low pass filter, and the rest of the data is furnished to a differential amplifier. The differential amplifier amplifies a difference between an output of the first low pass filter and an output of the second low pass filter, which is then supplied to an analog to digital converter. The analog to digital converter converts an output from the differential amplifier to digital data, which is then supplied to the compensation circuit. By doing so, a compensation value based on an output from the analog to digital converter is added to the following PCM sound data that is applied to the input terminal.

Claims

1. A class D amplifier comprising:

a PWM circuit for receiving input data and converting the input data to a PWM signal;

a low pass filter for passing low frequency components of the PWM signal;

a digital to analog converter for converting the input data to an analog signal;

a filter for only passing wanted frequency components of the analog signal from the digital to analog converter;

a difference detector for detecting a difference between a signal output from the low pass filter and a signal output from the filter;

a conversion unit for converting the detected difference to digital data; and

a feedback unit for feedbacking the converted digital data to an input of the PWM circuit.

2. A class D amplifier as recited in claim 1, further comprising a load connected to the low pass filter.

3. A class D amplifier as recited in claim 1, wherein the conversion unit is an analog digital converter.

4. A class D amplifier as recited in claim 1, wherein the conversion unit is a comparator.

5. A class D amplifier as recited in claim 1, further comprising a delay circuit for delaying the input data by a predetermine amount of time to apply the delayed input data to the digital to analog converter.

6. A class D amplifier as recited in claim 1, further comprising a damping compensation filter that is provided to the input of the PWM circuit for damping a peak caused by a resonance of the amplifier.

7. A class D amplifier as recited in claim 6, further comprising:

a test signal generator for generating a test signal whose frequency successively changes to provide the test signal to the PWM circuit;

an envelope measurement unit for measuring an envelope of the conversion unit; and

a coefficient measurement unit for measuring a frequency response of a signal from the envelope measurement unit to thereby obtain coefficients of the damping compensation filter.

8. A class D amplifier as recited in claim 1, further comprising:

an analog input terminal for receiving an analog signal;

a first switching unit for selectively supplying either the analog signal or the signal difference to the conversion unit; and

a second switching unit for selectively supplying either the input data or the converted digital data to the PWM circuit.

9. A class D amplifier as recited in claim 1, wherein the filter is an anti-aliasing filter that functions as a low pass filter.

10. A class D amplifier as recited in claim 2, wherein the load is a speaker.

11. A class D amplifier as recited in claim 2, wherein the feedback unit includes one or more integrators.

12. A class D amplifier comprising:

a PWM circuit for receiving input data and converting the input data to a PWM signal;

a power amplifier for amplifying the PWM signal;

a low pass filter for passing low frequency components of the amplified PWM signal to a load;

a digital to analog converter for converting the input data to an analog signal;

a first filter for only passing wanted frequency components of the analog signal from the digital to analog converter;

a second filter for only passing wanted frequency components of the amplified PWM signal to a load;

a difference detector for detecting a difference between first filter output signal output from the first filter and second filter output signal from the second filter;

a conversion unit for converting the detected signal difference to digital data; and

a feedback unit for feedbacking the converted digital data to an input of the PWM circuit.

14. A class D amplifier as recited in claim 12, wherein the conversion unit includes:

a dither generator for generating a dither signal;

an adder for adding the dither signal to an output of the difference detector;

a pulse width conversion unit for converting an output of the adder to a pulse width; and

a counter for converting the pulse width to digital data.

13. A class D amplifier comprising:

a first PWM circuit for receiving input data and converting the input data to a first PWM signal;

a power amplifier for amplifying the first PWM signal;

a low pass filter for passing low frequency components of the amplified first PWM signal to a load;

a second PWM circuit for converting the input data to a second PWM signal;

a first filter for only passing wanted frequency components of the second PWM signal;

a second filter for only passing wanted frequency components of the amplified first PWM signal from the power amplifier;

a difference detector for detecting a difference between a first filter output signal output from the first filter and a second filter output signal output from the second filter;

a conversion unit for converting the detected signal difference to digital data; and

a feedback unit for feedbacking the converted digital data to an input of the first PWM circuit.

15. A class D amplifier as recited in claim 13, wherein the conversion unit includes:

a dither generator for generating a dither signal;

an adder for adding the dither signal to an output of the difference detector;

a pulse width conversion unit for converting an output of the adder to a pulse width; and

a counter for converting the pulse width to digital data.

16. A class D amplifier comprising:

a PWM circuit for receiving input data and converting the input data to a PWM signal;

a power amplifier for amplifying the PWM signal;

a first low pass filter for passing low frequency components of the amplified PWM signal to a load;

a level shifter for level-shifting the amplified PWM signal from the power amplifier to produce a pulse width;

a counter for converting the pulse width from the level shifter to digital data;

a second low pass filter for passing low frequency components of the digital data from the counter; and

a feedback unit for feedbacking an output of the second low pass filter to an input of the PWM circuit.

17. A class D amplifier as recited in claim 16, further comprising:

a compensation circuit coupled to the PWM circuit for compensating quantization noise from the PWM circuit; and

an adder provided in place of the feedback unit for adding the output of the second low pass filter and the input data, by which an added result is applied to an input of the adder.

18. A class D amplifier as recited in claim 17, further comprising:

a memory provided in place of the second low pass filter for storing the digital data from the counter into a memory address that corresponds to the input data of the PWM circuit, wherein the digital data in the memory is read out based on the input data to be supplied to the adder.

19. A class D amplifier as recited in claim 16, further comprising:

a compensation circuit coupled to the PWM circuit for compensating quantization noise from the PWM circuit;

an arithmetic unit provided in place of the feedback unit for detecting a difference between the output of the second low pass filter and the input data, by which a detected result is added to the quantization noise to be applied to the compensation circuit.

20. A class D amplifier as recited in claim 16, further comprising:

a memory provided in place of the second low pass filter for storing the digital data from the counter into a memory address that corresponds to the input data of the PWM circuit,

wherein the digital data in the memory is read out based on the input data to be supplied to the arithmetic unit.

21. A class D amplifier as recited in claim 18, wherein when the digital data from the counter is stored in the memory, the storing is executed, after an average of data stored in addresses which are found around an address used for previously stored data is taken or after a low pass filter is applied.

22. A class D amplifier as recited in claim 20, wherein when the digital data from the counter is stored in the memory, the storing is executed, after an average of data stored in addresses which are found around an address used for previously stored data is taken or after a low pass filter is applied.

23. A class D amplifier comprising:

a PWM circuit for receiving input data and converting the input data to a PWM signal;

a power amplifier for amplifying the PWM signal;

a low pass filter for passing low frequency components of the amplified PWM signal to produce a low-pass filtered signal to a load;

a level shifter for level-shifting the amplified PWM signal from the power amplifier to produce a pulse width;

a counter for converting the pulse width from the level shifter to digital data;

a compensation circuit coupled to the PWM circuit for compensating quantization noise from the PWM circuit;

a memory for storing the digital data from the counter;

a first adder for adding an output from the memory and the input data, by which an added result is applied to the compensation circuit;

a digital to analog converter for converting the input data to an analog signal;

a filter for only passing wanted frequency components of the analog signal from the digital to analog converter to produce a filtered analog signal;

a difference detector for detecting for detecting a difference between the low-pass filtered signal to the load and the filtered analog signal;

a conversion unit for converting the detected signal difference to digital data; and

a second adder the digital data from the conversion unit to the compensation circuit,

wherein the digital data from the counter is stored based on a memory address that corresponds to the input data to the PWM circuit, and the stored data is read out based on the input data to the PWM circuit to be added to the first adder.

24. A class D amplifier comprising:

a PWM circuit for receiving input data and converting the input data to a PWM signal;

a low pass filter for passing low frequency components of the PWM signal to a load to produce a low pass filtered signal;

a compensation circuit coupled to the PWM circuit for compensating quantization noise from the PWM circuit;

a digital to analog converter for converting the input data to an analog signal;

a filter for only passing wanted frequency components of the analog signal from the digital to analog converter to produce a filtered analog signal;

a difference detector for detecting a difference between the low pass filtered signal to the load and the filtered analog signal from the filter;

a conversion unit for converting the detected signal difference to digital data; and

a digital filter for feedbacking the converted digital data to an input of the compensation circuit.

25. A class D amplifier as recited in claim 24, wherein the digital filter is an IIR filter.