Switch for integrated telecommunication networks

• US 20060209899A1
• Filed: 03/03/2006
• Published: 09/21/2006
• Est. Priority Date: 03/04/2005
• Status: Abandoned Application

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Rossi, Paolo, Gladiali, Giulio, Treu, Marisa, Cucchi, Silvio
• Application Number:
  US11/366,426
• Publication Number:
  US 20060209899A1
• Time in Patent Office: Days
• US Class Current: 370/498
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13076 Distributing frame, MDF, cross-connect switch
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13167 Redundant apparatus
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13296 Packet switching, X.25, frame relay
• CPC Class Codes: H04Q 2213/1334 Configuration within the switch
• CPC Class Codes: H04Q 2213/13353 Routing table, map memory

Abstract

It is disclosed a switch for telecommunication networks. It comprises: a time division multiplexing matrix provided with a number of matrix inputs and a number of matrix outputs; source address generators, connected to matrix outputs of the time division multiplexing matrix. It further comprises: input modules, each of said input modules being adapted to generate a fixed size block, said block comprising a number of packets, arranged according to a predefined order; matrix input processing modules, each of said matrix input processing modules being connected to an input module to receive therefrom said fixed size block, and each of said matrix input processing modules being further connected to a matrix input; and a dynamic provisioning module, which is adapted to receive from said matrix input processing modules routing information comprised in said packets, generate, according to said routing information, a dynamic routing table, and supply said dynamic routing table to the source address generators.

Claims

1. A switch for telecommunication networks, comprising:

a time division multiplexing matrix provided with a number of matrix inputs and a number of matrix outputs;

source address generators, connected to matrix outputs of the time division multiplexing matrix;

input modules, each of said input modules being adapted to generate a fixed size block, said block comprising a number of packets, arranged according to a predefined order;

matrix input processing modules, each of said matrix input processing modules being connected to an input module to receive therefrom said fixed size block, and each of said matrix input processing modules being further connected to a matrix input; and

a dynamic provisioning module, which is adapted to

receive from said matrix input processing modules routing information comprised in said packets,

generate, according to said routing information, a dynamic routing table, and

supply said dynamic routing table to the source address generators.

2. The switch according to claim 1, further comprising a static provisioning module which is adapted to supply a static routing table to said source address generators.

3. The switch according to claim 2, wherein said fixed size block further comprises a portion of time division multiplexing flow.

4. The switch according to claim 3, further comprising a clock module for recovering from said time division multiplexing flow a reference clock signal, and supplying said reference clock signal to source address generators.

5. The switch according to claim 1, wherein said routing information is sent to said dynamic provisioning module according to said predefined order.

6. The switch according to claim 1, wherein said predefined order corresponds to the order of matrix outputs to which packets are addressed.

7. The switch according to claim 1, wherein said time division multiplexing matrix comprises a memory, wherein said matrix inputs are adapted to write into said memory, and wherein said matrix outputs are adapted to read from said memory.

8. The switch according to claim 7, wherein each of said matrix inputs writes said packets into said memory according to said predefined order, in contiguous positions.

9. The switch according to claim 8, wherein said routing information comprise a packet size.

10. The switch according to claim 9, wherein said source addresses of said packets are generated according to said packet size.

11. The switch according to claim 1, wherein it is at least partially implemented in an application specific integrated circuit.

22. A network element comprising a switch claim 1.

12. A method of switching information flows in a telecommunication network, said method comprising:

generating fixed size blocks comprising a number of packets which are arranged according to a predefined order;

taking routing information from said packets,

generating, according to said routing information, a dynamic routing table;

generating source addresses according to said dynamic routing table; and

supplying said source addresses to matrix outputs of a time division multiplexing matrix.

13. The method according to claim 12, wherein the step of generating source addresses further comprises generating source addresses according to a static provisioning table.

14. The method according to claim 13, wherein the step of generating fixed size blocks comprises generating fixed size blocks comprising a portion of a time division multiplexing flow.

15. The method according to claim 14, further comprising:

recovering a reference clock signal from said time division multiplexing flow; and

timing the step of generating source addresses according to said reference clock signal.

16. The method according to claim 12, wherein the step of taking routing information comprises taking routing information according to said predefined order.

17. The method according to claim 12, wherein said predefined order corresponds to the order according to which packets are addressed.

18. The method according to claim 12, further comprising:

.

writing said information flows into a memory; and

reading from a memory said information flows.

19. The method according to claim 18, wherein the step of writing comprises writing said packets into said memory according to a predefined order, in contiguous positions.

20. The method according to claim 19, wherein said routing information comprise a packet size.

21. The method according to claim 20, wherein the step of generating source addresses according to said dynamic routing table comprises generating source addresses according to packet size.