METHODS AND SYSTEMS FOR IMPROVING MICROELECTRONICI/O CURRENT CAPABILITIES
First Claim
1. A semiconductor package assembly comprising a substrate, at least one integrated circuit chip mounted on said substrate, and at least one interconnect for connecting the substrate and said integrated circuit chip, and wherein the integrated circuit chip includes a via, the interconnect includes a solder ball extending into the via to help connect the circuit chip and the substrate, and the via has an increased diameter of about at least 55um to increase the electromigration lifetime of the solder ball.
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Accused Products
Abstract
Disclosed are microelectronic structures based on improved design and material combinations to provide improved current capabilities per I/O. The preferred embodiment of the invention uses a combination of one or more of the following: (1) Underbump metallurgy which enhances current per I/O by increasing via diameter or by having multiple via openings under BLM; (2) Thicker underbump metallurgy, where use of good conductor metallurgies can be used with increased thickness; (3) Utilizing larger via diameter under bump metallurgy, larger solder bump diameter and/or other current enhancing features for power and/or ground via connections; and (4) Using additives in Pb-free alloys to alter microstructure to minimize migration of atoms in the solder or at intermetallic transitions.
47 Citations
28 Claims
- 1. A semiconductor package assembly comprising a substrate, at least one integrated circuit chip mounted on said substrate, and at least one interconnect for connecting the substrate and said integrated circuit chip, and wherein the integrated circuit chip includes a via, the interconnect includes a solder ball extending into the via to help connect the circuit chip and the substrate, and the via has an increased diameter of about at least 55um to increase the electromigration lifetime of the solder ball.
- 5. A semiconductor package assembly comprising a substrate, at least one integrated circuit chip mounted on said substrate, and at least one interconnect for connecting the substrate and said integrated circuit chip, and wherein the interconnect includes at least one solder ball, the integrated circuit includes multiple via openings, and said at least one solder ball extends into all of said via openings to help connect the integrated circuit to the substrate, thereby to reduce the current density through said at least one solder ball.
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13. A method of assembling a semiconductor package, comprising the steps of:
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using solder bumps to help connect an integrated circuit chip to a substrate; and
providing the integrated circuit with a thicker, greater than 2 um, underbump metallurgy to enhance current carrying capability and limit current crowding. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method of designing a semiconductor package to include current enhancing features for power and/or ground connections, the method comprising the step of:
selecting the design of electromigration enhanced features for the connections by considering the following factors;
1. direction of electron flow through the connections;
2. amount of required current through the connections; and
3. degree of redundancy among the connections. - View Dependent Claims (20, 21, 22, 23)
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24. A method of assembling a semiconductor package, comprising the step of:
using solder bumps to help connect an integrated circuit chip to a substrate, including the step of using a Pb free alloy as a solder, the Pb-free alloy including additives to minimize migration of atoms in the solder or at intermetallic transitions. - View Dependent Claims (25, 26, 27, 28)
Specification