MOS transistor with laser-patterned metal gate, and method for making the same

• US 20060211187A1
• Filed: 08/11/2005
• Published: 09/21/2006
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Choi, Criswell, Rockenberger, Joerg, MacKenzie, J. Devin, Gudeman, Christopher
• Granted Patent: US 8,461,628 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32131 by physical means only
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A MOS transistor with a laser-patterned metal gate, and methods for its manufacture. The method generally includes forming a layer of metal-containing material on a dielectric film, wherein the dielectric film is on an electrically functional substrate comprising an inorganic semiconductor; laser patterning a metal gate from the metal-containing material layer; and forming source and drain terminals in the inorganic semiconductor in locations adjacent to the metal gate. The transistor generally includes an electrically functional substrate; a dielectric film on at least portions of the electrically functional substrate; a laser patterned metal gate on the dielectric film; and source and drain terminals comprising a doped inorganic semiconductor layer adjacent to the metal gate. The present invention advantageously provides MOS thin film transistors having reliable electrical characteristics quickly, efficiently, and/or at a low cost by eliminating one or more conventional photolithographic steps.

Claims

1. A method for making a MOS transistor, comprising the steps of:

a) forming a layer of metal-containing material on a dielectric film, wherein said dielectric film is on an electrically functional substrate comprising an inorganic semiconductor;

b) laser patterning a metal gate from said metal-containing material layer; and

c) forming source and drain is in said inorganic semiconductor in locations substantially adjacent to said metal gate.

2. The method of claim 1, wherein said step of forming said layer of metal-containing material comprises blanket depositing said metal-containing material.

3. The method of claim 2, said metal-containing material comprises a metal or metal alloy, and said blanket depositing step comprises sputtering said metal or metal alloy.

4. The method of claim 2, wherein said blanket depositing step comprises spin-coating an ink containing said metal-containing material.

5. The method of claim 2, wherein said metal-containing material comprises metal nanoparticles.

6. The method of claim 5, wherein said metal-containing material further comprises an organometallic precursor, an inorganic or organic reducing agent, a surface tension reducing agent, a surfactant, a binder and/or a thickening agent.

7. The method of claim 5, further comprising the step(s) of curing and/or annealing said metal nanoparticles before the step of laser patterning.

8. The method of claim 1, further comprising depositing a resist on said metal-containing material layer before said laser patterning step.

9. The method of claim 8, wherein said laser patterning step comprises irradiating said resist in locations corresponding to said metal gate.

10. The method of claim 8, wherein said laser patterning step comprises irradiating said resist in locations other than those locations corresponding to said metal gate.

11. The method of claim 8, further comprising the step of developing said resist.

12. The method of claim 11, further comprising the step of removing portions of said metal-containing material exposed by said developing step.

13. The method of claim 8, wherein said resist comprises a thermal resist, and said method further comprises the step of heating said resist after said laser patterning step.

14. The method of claim 13, further comprising the step of developing said resist.

15. The method of claim 1, wherein said metal-containing material comprises metal nanoparticles, and said laser patterning step comprises irradiating said metal nanoparticles sufficiently link or flue said metal nanoparticles to each other.

16. The method of claim 15, further comprising the step of removing non-irradiated metal-containing material.

17. The method of claim 16, further comprising the step of annealing the laser patterned metal gate sufficiently to improve its electrical, physical and/or adhesive properties.

18. The method of claim 1, wherein said metal-containing material comprises an ink containing one or more photosensitive or thermally sensitive initiators.

19. The method of claim 18, wherein said laser writing step comprises irradiating said metal-containing material sufficiently to change the solubility characteristics thereof in a subsequently-used developer.

20. The method of claim 19, further comprising the step of removing either the irradiated metal-containing material or a non-irradiated metal-containing material with said developer.

21. The method of claim 20, further comprising curing the patterned metal-containing material to form a patterned metal and/or metal alloy film.

22. The method of claim 19, wherein said metal-containing material comprises metal nanoparticles with ligands bound thereto, said ligands containing a photoreaction or thermally sensitive group or a group that is reactive with a photochemically or thermally generated species and that, after first-order photoreaction or reacting with said photochemically or thermally generated species materially changes the solubility characteristics of said metal-containing material in said developer.

23. The method of claim 1, wherein said metal-containing material layer forming step comprises printing a metal-containing ink onto said dielectric film.

24. The method of claim 23, wherein said printing step comprises inkjet printing, microspotting, stenciling, stamping, syringe dispensing, pump dispensing, screen printing, gravure printing, offset printing, or flexographic printing said metal-containing ink onto said dielectric film.

25. The method of claim 1, further comprising the step of wet etching exposed portions of said dielectric film using said metal gate as a mask.

26. The method of claim 1, wherein said inorganic semiconductor consists essentially of a Group IVA semiconductor.

27. The method of claim 26, wherein said source/drain terminals comprise a highly doped Group IVA layer with contact resistance of <

10<sub>−

3</sub> ohm cm².

28. The method of claim 1, further comprising the step of forming one or more first conductive structures in electric contact with each of said semiconductor source/drain terminals and said metal gate.

29. The method of claim 28, wherein said conductive structure forming step comprises printing an ink comprising a conductor precursor.

30. The method of claim 1, further comprising the step of forming said dielectric film on said inorganic semiconductor.

31. The method of claim 1, further comprising forming said semiconductor layer on an electrically inactive layer on said substrate.

32. The method of claim 31, wherein said semiconductor layer forming step comprises depositing a semiconductor ink onto said electrically inactive layer, then curing and/or annealing said semiconductor ink.

33. The method of claim 32, wherein said depositing step comprises printing said inorganic semiconductor ink onto said electrically inactive layer in a location corresponding to an active region of said MOS transistor.

34. The method of claim 1, wherein said electrically functional substrate comprises a dielectric layer on a metal substrate.

35. The method of claim 1, further comprising the step of depositing an insulator material over said MOS transistor.

36. An electric device, comprising:

a) a semiconductor substrate;

b) a dielectric film on at least portions of said semiconductor substrate;

c) a laser patterned metal gate on the dielectric film; and

d) source and drain terminals comprising a doped layer on or in said substrate, substantially adjacent to said metal gate.

37. The electronic device of claim 36, wherein each of said source and drain terminals has a border closest to said metal gate that is substantially aligned with a border of said metal gate.

38. The electronic device of claim 36, further comprising (i) one or more first conductors electrically connected to each of said source and drain terminals and (ii) a second conductor electrically connected to said gate metal layer.

39. The electronic device of claim 36, wherein said substrate comprises an electrically inert substrate and a semiconducting and/or transistor channel layer thereon.

40. The electronic device of claim 39, wherein said semiconducting and/or transistor channel layer comprises a lightly doped semiconductor.

41. The electronic device of claim 36, wherein said doped layer comprises an electrically active, polycrystalline Group IVA semiconductor layer.