Silicon oxide cap over high dielectric constant films

• US 20060211259A1
• Filed: 03/21/2005
• Published: 09/21/2006
• Est. Priority Date: 03/21/2005
• Status: Abandoned Application

• Current Assignee: ASM America Incorporated (ASM International NV)
• Original Assignee: ASM America Incorporated (ASM International NV)
• Inventors: Witte, Hilde De, Maes, Jan Willem, Pomarede, Christophe
• Application Number:
  US11/087,079
• Publication Number:
  US 20060211259A1
• Time in Patent Office: Days
• US Class Current: 438/762
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: C23C 16/405 of refractory metals or yttrium
• CPC Class Codes: C23C 16/452 by activating reactive gas streams before their introduction into the reaction chamber, e.g. by ionisation or addition of reactive species
• CPC Class Codes: C23C 16/45504 Laminar flow
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/482 using incoherent light, UV to IR, e.g. lamps
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method for forming an integrated circuit structure on a semiconductor substrate comprises depositing a high k gate dielectric material over the substrate using an atomic layer deposition process. A silicon oxide capping layer is deposited over the gate dielectric material in a rapid thermal chemical vapor deposition process. A gate electrode is formed over the silicon oxide capping layer.

Claims

1. A method for forming an integrated circuit structure on a semiconductor substrate comprising:

depositing a gate dielectric over the semiconductor substrate using an atomic layer deposition process, wherein the gate dielectric comprises a high k material;

depositing a silicon oxide layer over the gate dielectric material in a rapid thermal chemical vapor deposition process, using SiH₄ and N₂O as silicon and oxygen source gases, respectively; and

forming a gate electrode over the silicon oxide layer.

2. The method of claim 1, wherein SiH₄ is used as a silicon source gas for the deposition of the silicon oxide layer.

3. The method of claim 1, wherein N₂O is used as a oxygen source gas for the deposition of the silicon oxide layer.

4. The method of claim 1, wherein the silicon oxide layer comprises SiO₂.

5. The method of claim 1, wherein the silicon oxide layer comprises SiON.

6. The method of claim 1, wherein the silicon oxide layer is deposited at a rate that is between approximately 5 Å

min<sup>−

1</sup> and approximately 25 Å

min<sup>−

1</sup>.

7. The method of claim 1, wherein the silicon oxide layer is deposited at a temperature between approximately 500°

C. and approximately 800°

C.

8. The method of claim 1, wherein the silicon oxide layer is deposited at a temperature between approximately 600°

C. and approximately 700°

C.

9. The method of claim 1, further comprising growing a lower interface layer on the semiconductor substrate, the lower interface layer configured to form an interface between the semiconductor substrate and the gate dielectric.

10. The method of claim 9, wherein the lower interface layer comprises silicon oxide.

11. The method of claim 1, wherein the silicon oxide layer has a thickness between approximately 0.3 nm and approximately 2.0 nm.

12. The method of claim 1, wherein the gate dielectric comprises HfO₂.

13. The method of claim 1, wherein the gate dielectric comprises a metal oxide.

14. The method of claim 1, wherein the gate dielectric comprises a material having a dielectric constant of greater than approximately 7.

15. The method of claim 1, wherein the gate electrode comprises polycrystalline silicon.

16. A method of fabricating integrated circuits comprising:

providing a high k material;

depositing silicon oxide on the high k material in a rapid thermal chemical vapor deposition process; and

forming an electrode over the silicon oxide.

17. The method of claim 16, wherein the high k material is formed using an ALD process.

18. The method of claim 16, wherein the electrode is a gate electrode of a transistor structure.

19. The method of claim 16, wherein the electrode is an electrode of a capacitor structure.

20. The method of claim 16, wherein the silicon oxide is deposited at a rate that is between approximately 5 Å

min<sup>−

1</sup> and approximately 25 Å

min<sup>−

1</sup>.

21. The method of claim 16, wherein the silicon oxide layer is deposited at a temperature between approximately 500°

C. and approximately 800°

C.

22. The method of claim 16, further comprising forming an interface layer on a semiconductor substrate prior to providing the high k material.

23. The method of claim 16, further comprising growing an interface layer on a semiconductor substrate prior to providing the high k material, and wherein the interface layer comprises silicon oxide.

24. The method of claim 16, wherein SiH₄ and N₂O are used as silicon and oxygen sources, respectively, in depositing the silicon oxide.

25. The method of claim 16, wherein the silicon oxide is deposited to a thickness of between approximately 0.3 nm and approximately 2.0 nm.

26. The method of claim 16, wherein the silicon oxide is deposited for less than approximately 180 seconds.

27. The method of claim 16, wherein the silicon oxide is deposited for less than approximately 60 seconds.

28. The method of claim 16, wherein the silicon oxide is deposited for between approximately 10 seconds and approximately 135 seconds.

29. The method of claim 16, wherein the high k material comprises a metal oxide.

30. The method of claim 16, wherein the high k material comprises a material having a dielectric constant of greater than approximately 7.

31. The method of claim 16, wherein the high k material comprises a material having a dielectric constant of greater than approximately 10.

32. The method of claim 16, wherein the electrode comprises polycrystalline silicon.

33. A thin film transistor apparatus comprising:

a semiconductor substrate;

a gate dielectric material positioned over the semiconductor substrate, the gate dielectric material having a dielectric constant greater than approximately 7;

a silicon oxide capping layer positioned on the gate dielectric material; and

a gate electrode formed on the capping layer.

34. The apparatus of claim 33, wherein the capping layer has a thickness between approximately 0.3 nm and approximately 2.0 nm.

35. The apparatus of claim 33, wherein the capping layer has a thickness between approximately 0.3 nm and approximately 1.2 nm.

36. The apparatus of claim 33, wherein the gate dielectric material is in direct contact with the semiconductor substrate.

37. The apparatus of claim 33, wherein the gate electrode comprises polycrystalline silicon germanium.

38. The apparatus of claim 33, further comprising a lower interface layer positioned between the semiconductor substrate and the gate dielectric material.

39. The apparatus of claim 38, wherein the lower interface layer is selected from the group consisting of silicon oxide and silicon oxynitride.

40. The apparatus of claim 38, wherein the lower interface layer has a thickness between approximately 0.3 nm and approximately 1.2 nm.

41. The apparatus of claim 33, wherein the gate dielectric material comprises a metal oxide.

42. The apparatus of claim 33, wherein the gate dielectric material comprises a material having a dielectric constant greater than approximately 10.

43. The apparatus of claim 33, wherein the gate dielectric material is selected from the group consisting of zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, barium strontium titanate, strontium bismuth tantalate, and lanthanide oxides.

44. An integrated circuit comprising:

a layer of high k material having a first side and a second side opposite the first side;

an oxide capping layer contacting the first side of the high k layer; and

a conductor contacting the second side of the high k material.

45. The integrated circuit of claim 44, wherein the conductor is a capacitor electrode.

46. The integrated circuit of claim 44, wherein the conductor is a transistor gate electrode;

47. The integrated circuit of claim 46, wherein the high k layer is positioned over a semiconductor substrate.

48. The integrated circuit of claim 47, further comprising a lower interface layer positioned between the semiconductor substrate and the high k layer.

49. The integrated circuit of claim 48, wherein the lower interface layer is selected form the group consisting of silicon oxide and silicon oxynitride.

50. The integrated circuit of claim 48, wherein the lower interface layer has a thickness between approximately 0.3 nm and approximately 1.5 nm.

51. The integrated circuit of claim 46, wherein the transistor gate electrode comprises polycrystalline silicon.

52. The integrated circuit of claim 44, wherein the capping layer has a thickness between approximately 0.3 nm and approximately 2.0 nm.

53. The integrated circuit of claim 44, wherein the capping layer has a thickness between approximately 0.3 nm and approximately 1.2 nm.

54. The integrated circuit of claim 44, wherein the capping layer has a thickness between approximately 0.3 nm and approximately 1.0 nm.

55. The integrated circuit of claim 44, wherein the high k layer comprises a metal oxide.

56. The integrated circuit of claim 44, wherein the high k layer comprises a material having a dielectric constant greater than approximately 10.

57. The integrated circuit of claim 44, wherein the high k layer is selected from the group consisting of zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, barium strontium titanate, strontium bismuth tantalate, and lanthanide oxides.