Method of monitoring and/or controlling a semiconductor manufacturing apparatus and system therefor

• US 20060212156A1
• Filed: 05/24/2006
• Published: 09/21/2006
• Est. Priority Date: 09/06/2001
• Status: Active Grant

• Current Assignee: Akira Kagoshima, Daisuke Shiraishi, Hideyuki Yamamoto, Hiroyuki Kitsunai, Junichi Tanaka, Shoji Ikuhara, Toshio Masuda
• Original Assignee: Akira Kagoshima, Daisuke Shiraishi, Hideyuki Yamamoto, Hiroyuki Kitsunai, Junichi Tanaka, Shoji Ikuhara, Toshio Masuda
• Inventors: Tanaka, Junichi, Shiraishi, Daisuke, Ikuhara, Shoji, Yamamoto, Hideyuki, Kitsunai, Hiroyuki, Masuda, Toshio, Kagoshima, Akira
• Granted Patent: US 7,343,217 B2
• Time in Patent Office: Days
• US Class Current: 700/121
• CPC Class Codes: G05B 13/048 using a predictor
• CPC Class Codes: G05B 19/41865 characterised by job scheduling, process planning, material flow
• CPC Class Codes: G05B 2219/31357 Observer based fault detection, use model
• CPC Class Codes: G05B 2219/32058 Execute program as function of deviation from predicted state, result
• CPC Class Codes: G05B 23/024 Quantitative history assessment, e.g. mathematical relationships between available data; Functions therefor; Principal component analysis [PCA]; Partial least square [PLS]; Statistical classifiers, e.g. Bayesian networks, linear regression or correlation analysis; Neural networks
• CPC Class Codes: H01L 21/67276 Production flow monitoring, e.g. for increasing throughput program-control systems per se G05B19/00, e.g. total factory control G05B19/418
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A semiconductor processing apparatus for processing a semiconductor wafer includes a plurality of sensors for monitoring a processing state, a processing result input unit, a model equation generation unit to generate a model equation for predicting a processing result, a processing result prediction unit which predicts a processing result, and a process recipe control unit. Further, a system is provided which comprises the model equation generation unit is provided at a remote location, and transmits the generated prediction model equation to the semiconductor processing apparatus through a network to control the processing condition of the semiconductor processing apparatus by the process recipe control unit.

Claims

1. A semiconductor processing apparatus for processing a semiconductor wafer, comprising:

a plurality of sensors each for monitoring a processing state of said semiconductor processing apparatus;

a processing result input unit which inputs measured values for processing results of a semiconductor wafer processed by said semiconductor processing apparatus;

a model equation generation unit relying on sensed data acquired by said sensors and said measured values to generate a model equation for predicting a processing result using said sensed data as an explanatory variable;

a processing result prediction unit which predicts a processing result based on said model equation and said sensed data; and

a process recipe control unit which compares said predicted processing result with a previously set value to control a processing condition of said semiconductor processing apparatus such that a deviation between said predicted processing result and said previously set value is corrected;

wherein a system, which comprises said model equation generation unit to thereby generate the prediction model equation, is provided at a remote location, and said system transmits said generated prediction model equation to said semiconductor processing apparatus through a network to control the processing condition of said semiconductor processing apparatus by said process recipe control unit.

2. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 1, wherein said model equation unit generates the model equation using a partial least square (PLS) method.

3. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 1, wherein said model equation unit generates the model equation using robust regression for measured data in which any abnormal measured data is removed.

4. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 1, wherein a plurality of different performances are controlled, and said plurality of different performances include different etching performances.

5. A semiconductor processing apparatus for processing a semiconductor wafer according to claim 4, wherein the etching performance includes vertical etching or selectivity.