On-Chip Inter-Subsystem Communication

• US 20060212632A1
• Filed: 06/06/2006
• Published: 09/21/2006
• Est. Priority Date: 02/28/2001
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Apostol, George Jr., Kolluru, Mahadev S.
• Granted Patent: US 7,243,179 B2
• Time in Patent Office: Days
• US Class Current: 710/113
• CPC Class Codes: G06F 13/1621 by maintaining request order
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 2213/0038 System on Chip

Abstract

A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Claims

1. A data transfer block for use in an integrated circuit (IC) to interface an on-chip subsystem to an on-chip bus, the data transfer block comprising:

a first and a second outbound queue to facilitate staging of a first and a second plurality of outbound bus transactions for the on-chip subsystem, each of said outbound bus transactions including a bus arbitration priority; and

a first state machine coupled to the first and second outbound queues to service the first and second outbound queues by according the first queue a first outbound priority and the second queue a second outbound priority, and requesting for access to the on-chip bus for the staged outbound bus transactions based at least in part on accorded outbound priorities, where access to the on-chip bus is granted to requesting bus transactions based at least in part on the included bus arbitration priorities of the contending bus transactions.

2. The data transfer block of claim 1, wherein said data transfer block further comprises a configuration register coupled to said first state machine to store said first and second priorities to be accorded to said first and second outbound queues by said first state machine in servicing said first and second outbound queues.

3. The data transfer block of claim 1, wherein the data transfer block further comprises:

a first and a second inbound queue to facilitate staging of a first and a second plurality of inbound bus transactions for the on-chip subsystem, each of the inbound bus transaction including a bus arbitration priority and being granted access to the on-chip bus based at least in part on the included bus arbitration priority; and

a second state machine coupled to the first and second inbound queues to service the first and second inbound queues, bringing the staged inbound bus transactions to the attention of the on-chip subsystem, according the first inbound queue a first inbound priority and the second inbound queue a second inbound priority.

4. The data transfer block of claim 3, wherein said data transfer block further comprises a configuration register coupled to said second state machine to store said first and second inbound priorities to be accorded to said first and second inbound queues by said second state machine in servicing said first and second inbound queues.

5. A data transfer block for use in an integrated circuit (IC) to interface an on-chip subsystem to an on-chip bus, the data transfer block comprising:

a first and a second inbound queue to facilitate staging of a first and a second plurality of inbound bus transactions for the on-chip subsystem, each of the inbound bus transactions including a bus arbitration priority and being granted access to the on-chip bus based at least in part on the included bus arbitration priority; and

a state machine coupled to the first and second inbound queues to service the first and second inbound queues by according the first inbound queue a first inbound priority and the second inbound queue a second inbound priority and bringing the staged inbound bus transactions to the attention of the on-chip subsystem based at least in part on the accorded inbound priorities.

6. The data transfer block of claim 5, wherein said data transfer block further comprises a configuration register coupled to said state machine to store said first and second inbound priorities to be accorded to said first and second inbound queues by said state machine in servicing said first and second inbound queues.

7. A subsystem of an integrated circuit, the subsystem comprising:

core subsystem logic; and

a data transfer unit to couple the core subsystem logic to an on-chip bus of the integrated circuit, the data transfer unit including;

a first and a second outbound queue to facilitate staging of a first and a second plurality of outbound bus transactions for the core subsystem logic, each of said outbound bus transactions including a bus arbitration priority; and

a first state machine coupled to the first and second outbound queues to service the first and second outbound queues by according the first queue a first outbound priority and the second queue a second outbound priority, and requesting for access to the on-chip bus for the staged outbound bus transactions based at least in part on accorded outbound priorities, where access to the on-chip bus is granted to requesting bus transactions based at least in part on the included bus arbitration priorities of the contending bus transactions.

8. The subsystem of claim 7, wherein said data transfer unit further comprises a configuration register coupled to said first state machine to store said first and second priorities to be accorded to said first and second outbound queues by said first state machine in servicing said first and second outbound queues.

9. The subsystem of claim 7, wherein the data transfer unit further comprises:

a first and a second inbound queue to facilitate staging of a first and a second plurality of inbound bus transactions for the core subsystem logic, each of the inbound bus transaction including a bus arbitration priority and being granted access to the on-chip bus based at least in part on the included bus arbitration priority; and

a second state machine coupled to the first and second inbound queues to service the first and second inbound queues, bringing the staged inbound bus transactions to the attention of the core subsystem logic, according the first inbound queue a first inbound priority and the second inbound queue a second inbound priority.

10. The subsystem of claim 9, wherein said data transfer block further comprises a configuration register coupled to said second state machine to store said first and second inbound priorities to be accorded to said first and second inbound queues by said second state machine in servicing said first and second inbound queues.

11. The subsystem of claim 7, wherein the subsystem is a memory controller, a security engine, a voice processor, a collection of peripheral device controllers, a framer processor, or a network media access controller.

12. A subsystem of an integrated circuit, the subsystem comprising:

core subsystem logic; and

a data transfer unit to couple the core subsystem logic to an on-chip bus of the integrated circuit, the data transfer unit including;

a first and a second inbound queue to facilitate staging of a first and a second plurality of inbound bus transactions for the core subsystem logic, each of the inbound bus transaction including a bus arbitration priority and being granted access to the on-chip bus based at least in part on the included bus arbitration priority; and

a state machine coupled to the first and second inbound queues to service the first and second inbound queues by according the first inbound queue a first inbound priority and the second inbound queue a second inbound priority and bringing the staged inbound bus transactions to the attention of the on-chip subsystem based at least in part on the in bound priority.

13. The subsystem of claim 12, wherein said data transfer unit further comprises a configuration register coupled to said state machine to store said first and second inbound priorities to be accorded to said first and second inbound queues by said state machine in servicing said first and second inbound queues.

14. The subsystem of claim 12, wherein the subsystem is a selected one of a memory controller, a security engine, a voice processor, a collection of peripheral device controllers, a framer processor, and a network media access controller.