Posted write buffers and method of posting write requests in memory modules
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Accused Products
Abstract
A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.
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Citations
50 Claims
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1-13. -13. (canceled)
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14. A memory hub, comprising:
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a link interface receiving memory requests;
a memory device interface operable to output memory requests and to receive read data responsive to the memory requests output by the memory device interface;
a posted write buffer coupled to the link interface and the memory device interface, the posted write buffer being operable to store write memory requests and to subsequently couple the write memory requests to the memory device interface; and
a read request path operable to couple read memory requests from the link interface to the memory device interface and to couple read data from the memory device interface to the link interface. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A computer system, comprising:
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a central processing unit (“
CPU”
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a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each of the memory modules comprising;
a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a posted write buffer coupled to the link interface and the memory device interface, the posted write buffer being operable to store write memory requests and to subsequently couple the write memory requests to the memory device interface; and
a read request path operable to couple read memory requests from the link interface to the memory device interface and to couple read data from the memory device interface to the link interface; and
a communications link coupled between the system controller and each of the memory modules for coupling memory requests and read data between the system controller and the memory modules in the respective memory modules. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. In a computer system, a method of reading data from a plurality of memory modules, comprising:
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receiving memory requests at each of the plurality of memory modules, the memory requests requesting access to a memory device in the memory module, the memory requests including read requests and write requests;
coupling at least some of the read memory requests to the memory device in the memory module receiving the read request;
coupling read data from the memory module responsive to the read memory request;
accumulating the write requests in the memory module without immediately coupling the write requests to the memory devices in the memory module receiving the write request; and
subsequently coupling each of the accumulated write requests to the memory device in the memory module receiving the write request. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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Specification