Dual thread processor

• US 20060212687A1
• Filed: 03/18/2005
• Published: 09/21/2006
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Chen, Hong-Yi
• Granted Patent: US 8,195,922 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register file including a plurality of banks corresponding to the plurality of processor threads. Each bank is operable to store data associated with a corresponding processor thread. The processor can include a set of registers corresponding to each of a plurality of processor threads. Each register within a set is located either before or after a pipeline stage of the processor.

Claims

1. A processor, comprising:

a pipeline stage including,

a first input register;

a second input register;

a first output register;

a second output register;

a first selector in communication with the first input register and the second input register;

a second selector in communication with the first output register and the second output register; and

a controller operable to control switching of the first and second selectors such that data associated with a first processor thread pass through the first input register, the pipeline stage, and the first output register during a time that the first processor thread is being processed, and data associated with a second processor thread pass through the second input register, the pipeline stage, and the second output register during a time that the second processor thread is being processed,

wherein the first input register and the first output register are operable to store a state of the first processor thread, and wherein the second input register and the second output register are operable to store a state of the second processor thread.

2. The processor of claim 1, wherein the first selector includes a multiplexer and the second selector includes a de-multiplexer.

3. The processor of claim 1, wherein the pipeline stage includes one of an instruction fetch unit, decode logic, issue logic, execution unit, read logic, or write logic.

4. The processor of claim 1, wherein the controller controls switching of the first and second selectors based on input defining processor time to be allocated to each of the first processor thread and the second processor thread.

5. The processor of claim 4, wherein the controller is operable to control switching of the first and second selectors dynamically during execution of a program.

6. The processor of claim 4, wherein the controller controls switching of the first and second selectors statically based on a pre-determined processor time allocation for each of the first processor thread and the second processor thread.

7. The processor of claim 1, further comprising:

a first interrupt handling routine to handle an interrupt request associated with the first processor thread; and

a second interrupt handling routine to handle an interrupt request associated with the second processor thread.

8. The processor of claim 7, wherein the first interrupt handling routine and the second interrupt handling routine have separate entry points.

9. The processor of claim 1, further comprising:

a first exception handling routine to handle an exception request associated with the first processor thread; and

a second exception handling routine to handle an exception request associated with the second processor thread.

10. The processor of claim 1, further comprising a single exception handling routine or a single interrupt handling routine to respectively handle substantially all exception requests or substantially all interrupt requests associated with both the first processor thread and the second processor thread.

11. The processor of claim 1, further comprising a set of registers corresponding to each of a plurality of processor threads, each register within a set being located either before or after a pipeline stage of the processor, and wherein the controller is operable to perform a context switch among the plurality of processor threads, including storing a state of a currently executing processor thread in a corresponding set of registers, and loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread.

12. A processor, comprising:

a set of registers corresponding to each of a plurality of processor threads, each register within a set being located either before or after a pipeline stage of the processor; and

a programmable controller operable to perform a context switch among the plurality of processor threads, including storing a state of a currently executing processor thread in a corresponding set of registers, and loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread.

13. The processor of claim 12, wherein the programmable controller is operable to perform the context switch at an end of an instruction cycle.

14. The processor of claim 12, further comprising a register file including a plurality of banks corresponding to each of the plurality of processor threads, each bank operable to store data associated with a corresponding processor thread.

15. The processor of claim 12, further comprising a plurality of program counters, each program counter operable to indicate an execution status of a corresponding processor thread.

16. The processor of claim 12, further comprising a plurality of interrupt handling routines corresponding to the plurality of processor threads, wherein each interrupt handling routine handles an interrupt request associated with a corresponding processor thread.

17. The processor of claim 16, wherein each of the plurality of interrupt handling routines have separate entry points.

18. The processor of claim 12, further comprising a plurality of exception handling routines corresponding to the plurality of processor threads, wherein each exception handling routine handles an exception request associated with a corresponding processor thread.

19. The processor of claim 12, further comprising a single exception handling routine or a single interrupt handling routine to respectively handle substantially all exception requests or substantially all interrupt requests associated with the plurality of processor threads.

20. A method comprising:

providing a first processor thread for instruction execution;

providing a second processor thread for instruction execution;

processing the first processor thread; and

performing a context switch from the first processor thread to the second processor thread including,

storing a state of the first processor thread in a first set of registers corresponding to the first processor thread; and

loading a state of the second processor thread from a second set of registers corresponding to the second processor thread.

21. The method of claim 20, wherein storing a state of a given processor thread within a corresponding set of registers includes storing data corresponding to a pipeline stage of a processor.

22. The method of claim 20, further comprising:

receiving input changing the processor time allocation; and

performing a context switch among the first and second processor threads based on the changed processor time allocation.

23. The method of claim 20, wherein performing a context switch includes performing a context switch dynamically during execution of a program.

24. The method of claim 20, wherein performing a context switch includes performing a context switch statically based on a pre-determined processor time allocation for each of the first processor thread and the second processor thread.

25. The method of claim 20, further comprising:

using a first interrupt handling routine to handle an interrupt request associated with the first processor thread; and

using a second interrupt handling routine to handle an interrupt request associated with the second processor thread.

26. The method of claim 25, wherein the first interrupt handling routine and the second interrupt handling routine have separate entry points.

27. The method of claim 20, further comprising:

using a first exception handling routine to handle an exception request associated with the first processor thread; and

using a second exception handling routine to handle an exception request associated with the second processor thread.

28. The method of claim 20, further comprising using a single exception handling routine or a single interrupt handling routine to respectively handle substantially all exception requests and substantially all interrupt requests associated with the first processor thread and the second processor thread.

29. A processor comprising:

an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads;

a decoder responsive to the instruction fetch unit;

issue logic responsive to the decoder; and

a register file including a plurality of banks corresponding to the plurality of processor threads, each bank operable to only store data associated with a corresponding processor thread.

30. The processor of claim 29, wherein the data includes operands or results of executed instructions associated with a given processor thread.

31. The processor of claim 29, further comprising a controller in communication with the instruction fetch unit, the controller operable to determine a processor thread from which a next instruction will be fetched by the instruction fetch unit.

32. The processor of claim 31, further comprising:

a set of registers corresponding to each of the plurality of processor threads, each register within a set being located either before or after a pipeline stage of the processor, wherein

the controller is operable to perform a context switch among the plurality of processor threads, including storing a state of a currently executing processor thread in a corresponding set of registers, and loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread.

33. The processor of claim 31, wherein the controller includes a plurality of thread allocation counters corresponding to the plurality of processor threads, each thread allocation counter containing a value representing how much processor time is to be allocated for a respective processor thread.

34. The processor of claim 31, wherein the controller is operable to perform a context switch including switching a selector that is in communication with the instruction fetch unit.

35. The processor of claim 34, wherein the selector includes a multiplexer or a de-multiplexer.

36. The processor of claim 34, wherein the controller is operable to control switching of the selector dynamically during execution of a program.

37. The processor of claim 34, wherein the controller is operable to control switching of the selector statically based on a pre-determined processor time allocation for each of the plurality of processor threads.

38. The processor of claim 29, wherein each of the plurality of processor threads has an associated exception handling routine for handling exceptions that is separate and independent from exception handling routines associated with other processor threads.

39. The processor of claim 29, wherein each of the plurality of processor threads has an associated interrupt handling routine for handling interrupts that is separate and independent from interrupt handling routines associated with other processor threads.

40. The processor of claim 39, wherein each of the plurality of interrupt handling routines has a separate entry point.

41. A method, comprising:

providing a plurality of processor threads; and

performing a context switch among the plurality of processor threads including,

storing a state of a currently executing processor thread in a corresponding set of registers; and

loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread.

42. The method of claim 41, wherein performing a context switch includes performing the context switch at an end of an instruction cycle.

43. The method of claim 41, further comprising storing data associated with a given processor thread in a corresponding bank of a register file.

44. The method of claim 41, further comprising indicating an execution status of a corresponding processor thread.

45. The method of claim 41, further comprising handling an interrupt request associated with a given processor thread using an interrupt handling routine that is separate from interrupt handling routines associated with other ones of the plurality of processor threads.

46. The method of claim 45, wherein each interrupt handling routine has a separate entry point.

47. The method of claim 41, further comprising handling an exception request associated with a given processor thread using an exception handling routine that is separate from exception handling routines associated with other ones of the plurality of processor threads.

48. The method of claim 41, further comprising handling an exception request or an interrupt request associated with substantially all of the plurality of processor threads respectively using a single exception handling or a single interrupt handling routine.

49. A method, comprising:

fetching instructions associated with a plurality of processor threads;

decoding the instructions;

issuing the instructions to an execution unit; and

storing data associated with an issued instruction of a given processor thread within a corresponding bank of a register file, wherein each bank only stores data associated with a corresponding processor thread.

50. The method of claim 49, wherein the data includes operands or results of executed instructions associated with a given processor thread.

51. The method of claim 49, further comprising determining a processor thread from which a next instruction will be fetched.

52. The method of claim 51, further comprising performing a context switch among the plurality of processor threads including,

storing a state of a currently executing processor thread in a corresponding set of registers;

and

loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread.

53. The method of claim 51, further comprising providing a plurality of thread allocation counters corresponding to the plurality of processor threads, each thread allocation counter containing a value representing how much processor time is to be allocated for a respective processor thread.

54. The method of claim 51, wherein performing a context switch includes performing a context switch dynamically during execution of a program.

55. The method of claim 51, wherein performing a context switch includes performing a context switch statically based on a pre-determined processor time allocation for each of the plurality of processor threads.

56. The method of claim 49, further comprising handling an interrupt request associated with a given processor thread using an interrupt handling routine that is separate from interrupt handling routines associated with other ones of the plurality of processor threads.

57. The method of claim 56, wherein each interrupt handling routine has a separate entry point.

58. The method of claim 49, further comprising handling an exception request associated with a given processor thread using an exception handling routine that is separate from exception handling routines associated with other ones of the plurality of processor threads.

59. The method of claim 49, further comprising handling an exception request or an interrupt request associated with substantially all of the plurality of processor threads respectively using a single exception handling or a single interrupt handling routine.