Method and apparatus for a computing system having an active sleep mode CPU that uses the Cache of a normal active mode CPU

• US 20060212733A1
• Filed: 05/18/2006
• Published: 09/21/2006
• Est. Priority Date: 08/14/2002
• Status: Active Grant

• Current Assignee: Tony G. Hamilton
• Original Assignee: Tony G. Hamilton
• Inventors: Hamilton, Tony G.
• Granted Patent: US 7,734,936 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache of a high end central processing unit that caches normal active mode software instructions executed by the high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.

Claims

1. An apparatus, comprising:

a) a high end computing system, said high end computing system further comprising a first central processing unit and a graphics controller, said high end system active during a normal active mode; and

b) a low end computing system, said low end computing system further comprising a second central processing unit that is coupled to said first central processing unit, said low end computing system not comprising a graphics controller, said low end computing system having less power consumption than said high end computing system, said low end computing system active during an active sleep mode, said first central processing unit having a cache, said cache accessible to said second central processing unit, said cache located in said first central processing unit.

2. The apparatus of claim 1 wherein said high end computing system and said low end computing system share at least one I/O component.

3. The apparatus of claim 2 wherein said I/O component further comprises a wireless transceiver.

4. The apparatus of claim 2 wherein said I/O component further comprises a non volatile data storage device.

5. The apparatus of claim 4 wherein said non volatile data storage device further comprises a read only memory (ROM).

6. The apparatus of claim 4 wherein said non volatile data storage device further comprises a magnetic hard disk drive.

7. The apparatus of claim 4 wherein said non volatile data storage device further comprises a FLASH memory.

8. The apparatus of claim 1 wherein said cache is configured to store software instructions that are executed by said second central processing unit during said active sleep mode.

9. The apparatus of claim 1 wherein said cache is also configured to store data that is used by said second central processing unit to execute said software.

10. The apparatus of claim 1 wherein said low computing system and said high end computing system share the same display unit.

11. The apparatus of claim 1 wherein said high end computing system further comprises a memory controller.

12. The apparatus of claim 1 wherein said first central processing unit and said second processing unit are integrated onto the same semiconductor chip.

13. The apparatus of claim 12 wherein said first central processing unit and said second processing unit share circuitry on said semiconductor chip.

14. A method, comprising:

transitioning a computing system from a normal active mode to an active sleep, said transitioning comprising;

storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache of a high end central processing unit that cached normal active mode software instructions that were executed by said high end central processing unit during said normal active mode, said active sleep mode software instructions to be executed by said low end central processing unit during said active sleep mode, said computing system consuming less power during said active sleep mode than during said normal active mode; and

placing a graphics controller into a low power state in which said graphics controller will not perform graphics processing tasks that it performed in said normal active mode.

15. The method of claim 14 further comprising executing at least a portion of said active sleep mode instructions in order to wirelessly receive information during said active sleep mode.

16. The method of claim 15 further comprising executing at least a second portion of said active sleep mode instructions in order to decompress said information after it has been received.

17. The method of claim 15 further comprising transferring said information from a wireless interface to said on chip cache during said active sleep mode.

18. The method of claim 14 further comprising executing at least a portion of said active sleep mode instructions in order to store said information to a non volatile storage device.

19. The method of claim 17 wherein said non volatile storage device further comprises a magnetic hard disk drive.

20. The method of claim 17 further comprising executing at least a second portion of said active sleep mode instructions in order to compress said information before it is stored.

21. The method of claim 17 further comprising transferring said information from said on chip cache to said non volatile storage device.

22. The method of claim 18 further comprising executing at least a portion of said active sleep mode instructions in order to display information on a display unit.