Real-time control apparatus having a multi-thread processor

• US 20060212853A1
• Filed: 03/18/2005
• Published: 09/21/2006
• Est. Priority Date: 03/18/2005
• Status: Abandoned Application

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Application Number:
  US11/084,386
• Publication Number:
  US 20060212853A1
• Time in Patent Office: Days
• US Class Current: 717/131
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

In one implementation, a real-time controller is provided. The real-time controller includes a multi-thread processor adapted to execute at least two threads of program code. The multi-thread processor includes an execution pipeline, and a thread control unit to control the execution pipeline to execute media processing related program code as a first thread and system level program code as a second thread.

Claims

1. A hard disk controller comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute servo related program code as a first thread and system level program code as a second thread.

2. The hard disk controller of claim 1, further comprising a memory to store the servo related program code and the system level program code.

3. The hard disk controller of claim 2, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

4. The hard disk controller of claim 1, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

5. The hard disk controller of claim 1, wherein the system level program code comprises at least one of disk drive data capture program code, error correction program code, host protocol management program code, cache management program code, or defect manager program code.

6. The hard disk controller of claim 5, wherein the host protocol management program code manages at least one of the following protocols ATA, USB, SATA, SAS, FC, CE-ATA, or SDIO.

7. The hard disk controller of claim 1, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

8. The hard disk controller of claim 7, wherein the second multi-thread processor executes a given thread of program code not executed by the first multi-thread processor.

9. The hard disk controller of claim 1, further comprising a read channel.

10. A hard disk drive comprising:

a magnetic medium;

a read/write head to read from the magnetic medium and write to the magnetic medium; and

the hard disk controller of claim 9, wherein the hard disk controller is in communication with the read/write head.

11. A host computer comprising:

the hard disk drive of claim 10;

a memory; and

a processor in communication with the hard disk drive and the memory.

12. A DVD controller comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute servo related program code as a first thread and system level program code as a second thread.

13. The DVD controller of claim 12, further comprising a memory to store the servo related program code and the system level program code.

14. The DVD controller of claim 13, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

15. The DVD controller of claim 13, wherein the system level program code includes audio processing program code, and wherein the thread control unit further controls the execution pipeline to execute the audio processing program code as a third thread.

16. The DVD controller of claim 12, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

17. The DVD controller of claim 12, wherein the system level program code comprises at least one of DVD data capture program code, error correction program code, video processing program code, audio processing program code, host protocol management program code, cache management program code, defect manager program code, or encryption and security management program code.

18. The DVD controller of claim 17, wherein the host management program code manages at least one of the following protocols ATA, USB, SATA, SAS, FC, CE-ATA, or SDIO.

19. The DVD controller of claim 12, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

20. The DVD controller of claim 12, further comprising a read channel.

21. A DVD drive comprising:

a read device to read from an optical media; and

the DVD controller of claim 20, wherein the DVD controller is in communication with the read device.

22. A host computer comprising:

the DVD drive of claim 21;

a memory; and

a processor in communication with the DVD drive and the memory.

23. A DVD player comprising:

the DVD drive of claim 21;

a processor in communication with the DVD drive; and

an interface to communicate with a video output device.

24. A media player device comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute media processing related program code as a first thread and system level program code as a second thread.

25. The media player device of claim 24, wherein the media processing related program code comprises audio related program code.

26. The media player device of claim 24, wherein the media processing related program code comprises video related program code.

27. The media player device of claim 24, further comprising a memory storing the media processing related program code and the system level program code.

28. The media player device of claim 27, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

29. The media player device of claim 24, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

30. The media player device of claim 24, wherein the system level program code comprises at least one of servo related program code, disk drive data capture program code, error correction program code, video processing program code, audio processing program code, cache management program code, defect manager program code, or encryption and security management program code.

31. The media player device of claim 24, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

32. The media player device of claim 24, further comprising:

a storage medium to store at least one of audio or video data thereon; and

an output device to output the at least one of the audio or video data.

33. The media player device of claim 32, wherein the audio data is selected from the group consisting of MP3, EPAC™

, QDesign Music playback, AAC, Liquid Audio, MS Audio, Dolby Digital, RA, FLAC or WMA.

34. A cellular WLAN system comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute cellular communication related program code as a first thread and system level program code as a second thread.

35. The cellular WLAN system of claim 34, wherein the cellular communication related program code relates to one or more of the following protocols CDMA, G3, or GSM.

36. The cellular WLAN system of claim 34, further comprising a memory to store the cellular communication related program code and the system level program code.

37. The cellular WLAN system of claim 36, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

38. The cellular WLAN system of claim 34, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

39. The cellular WLAN system of claim 34, wherein the system level program code includes at least one of menu program code, display program code, MAC program code, WLAN program code, network communication program code, error correction program code, video processing program code, audio processing program code, host protocol management program code, cache management program code, defect manager program code, encryption/decryption program code, compression/decompression program code, wireless/wired communication program code or security management program code.

40. The cellular WLAN system of claim 34, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

41. A VoIP system comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute voice processing related program code as a first thread and system level program code as a second thread.

42. The VoIP system of claim 41, further comprising a memory to store the voice processing related program code and the system level program code.

43. The VoIP system of claim 42, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

44. The VoIP system of claim 41, wherein the thread control unit further controls the execution pipeline to execute codec related program code as a third thread.

45. The VoIP system of claim 41, wherein the voice processing related program code is program code associated with processing voice signals for conversion to a suitable form for transmission over a network.

46. The VoIP system of claim 41, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

47. The VoIP system of claim 41, wherein the system level program code includes at least one of MAC program code, WLAN program code, network communication program code, error correction program code, video processing program code, audio processing program code, host protocol management program code, cache management program code, defect manager program code, encryption/decryption program code, compression/decompression program code, wireless/wired communication program code or security management program code.

48. The VoIP system of claim 41, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

49. A wireless network device comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute wireless networking related program code as a first thread and system level program code as a second thread.

50. The wireless network device of claim 49, wherein the system level program code includes at least one of MAC program code, WLAN program code, network communication program code, error correction program code, video processing program code, audio processing program code, host protocol management program code, cache management program code, defect manager program code, encryption/decryption program code, compression/decompression program code, wired communication program code or security management program code.

51. The wireless network device of claim 49, further comprising a memory to store the wireless networking related program code and the system level program code.

52. The wireless network device of claim 51, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

53. The wireless network device of claim 49, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

54. The wireless network device of claim 49, wherein the wireless networking related program code includes at least one of routing program code, network program code, access point program code, repeater program code, security program code, or program code implementing a wireless communication protocol.

55. The wireless network device of claim 49, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

56. The wireless network device of claim 49, wherein the wireless network device is one of a wireless router or a wireless access point.

57. A wireless television system comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute media related program code as a first thread and system level program code as a second thread.

58. The wireless television system of claim 57, wherein the media related program code includes at least one of video processing program code, or audio processing program code.

59. The wireless television system of claim 57, further comprising a memory to store the media related program code and the system level program code.

60. The wireless television system of claim 59, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

61. The wireless television system of claim 57, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

62. The wireless television system of claim 57, wherein the system level program code includes at least one of MAC program code, WLAN program code, network communication program code, error correction program code, video processing program code, audio processing program code, host protocol management program code, cache management program code, defect manager program code, encryption/decryption program code, compression/decompression program code, wired/wireless communication program code or security management program code.

63. The wireless television system of claim 57, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

64. A broadband modem comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute broadband communication related program code as a first thread and system level program code as a second thread.

65. The broadband modem of claim 64, wherein the system level program code includes at least one of MAC program code, WLAN program code, network communication program code, error correction program code, video processing program code, audio processing program code, host protocol management program code, cache management program code, defect manager program code, encryption/decryption program code, compression/decompression program code, wired/wireless communication program code or security management program code.

66. The broadband modem of claim 64, further comprising a memory to store the broadband communication related program code and the system level program code.

67. The broadband modem of claim 66, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

68. The broadband modem of claim 64, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

69. The broadband modem of claim 64, wherein the broadband communication related program code includes cable communication program code, DSL communication program code, or satellite communication program code.

70. The broadband modem of claim 64, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

71. A wired router comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute networking related program code as a first thread and system level program code as a second thread.

72. The wired router of claim 71, wherein the system level program code includes at least one of MAC program code, WLAN program code, network communication program code, error correction program code, video processing program code, audio processing program code, host protocol management program code, cache management program code, defect manager program code, encryption/decryption program code, compression/decompression program code, wireless communication program code or security management program code.

73. The wired router of claim 71, further comprising a memory to store the networking related program code and the system level program code.

74. The wired router of claim 73, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

75. The wired router of claim 71, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

76. The wired router of claim 71, wherein the networking related program code includes at least one of routing program code, access point program code, security program code, repeater program code or virtual private networking program code.

77. The wired router of claim 71, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute first real-time program code as a third thread and second real-time program code as a fourth thread.

78. A real-time controller comprising:

a multi-thread processor adapted to execute at least two threads of program code, the multi-thread processor including,

an execution pipeline, and

a thread control unit to control the execution pipeline to execute first real-time program code as a first thread and second real-time program code as a second thread.

79. The real-time controller of claim 78, further comprising a memory to store the first real-time program code and the second real-time program code.

80. The real-time controller of claim 79, wherein the memory further stores user provided program code, and wherein the thread control unit further controls the execution pipeline to execute the user provided program code as a third thread.

81. The real-time controller of claim 78, wherein the execution pipeline comprises:

an instruction fetch unit;

a decoder responsive to the instruction fetch unit;

an issue unit responsive to the decoder; and

an execution unit responsive to the issue unit.

82. The real-time controller of claim 78, further comprising:

a second multi-thread processor adapted to execute at least two threads of program code, the second multi-thread processor including,

a second execution pipeline, and

a second thread control unit to control the second execution pipeline to execute third real-time program code as a third thread and fourth real-time program code as a fourth thread.

83. The real-time controller of claim 78, wherein the first real time code is video processing program code and the second real time code is audio program code.

84. A method comprising:

providing a first real-time program code;

providing a second real-time program code;

executing the first real-time program code with a first processor thread though an execution pipeline of a multi-thread processor; and

executing the second real-time program code with a second processor thread though the execution pipeline of the multi-thread processor.

85. The method of claim 84, further comprising storing the first real-time program code and the second real-time program code.

86. The method of claim 85, further comprising:

storing user provided program code; and

executing the user provided program code with a third processor thread though the execution pipeline of the multi-thread processor.