Readout technique for increasing or maintaining dynamic range in image sensors

• US 20060214085A1
• Filed: 03/24/2005
• Published: 09/28/2006
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Olsen, Espen A., Moholt, Jorgen
• Granted Patent: US 7,297,917 B2
• Time in Patent Office: Days
• US Class Current: 250/208.100
• CPC Class Codes: H04N 23/76 by influencing the image signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

The apparatus and method provide a readout technique and circuit for increasing or maintaining dynamic range of an image sensor. The readout technique and circuit process each pixel individually based on the magnitude of the readout signal. The circuit includes a gain amplifier amplifying the readout analog signal, a level detection circuit for determining the signal'"'"'s magnitude, a second gain amplifier applying a gain based on the signal magnitude and an analog-to-digital converter digitizing the signal and a circuit for multiplying or dividing the signal. The method and circuit allow for a lower signal-to-noise ratio while increasing the dynamic range of the imager.

Claims

1. A pixel readout circuit for an imager comprising:

a first gain amplifier for amplifying a signal from a pixel array;

a signal level determining circuit for determining a gain factor based on a level of the amplified signal;

a second variable gain amplifier, connected to said signal level determining circuit, for amplifying the signal from the first gain amplifier using the determined gain factor; and

an analog-to-digital converter for digitizing an output of the second gain amplifier.

2. The readout circuit according to claim 1, further comprising a circuit for multiplying or dividing an output of said analog-to-digital converter.

3. The readout circuit according to claim 1, wherein said signal level determining circuit further comprises:

a level detection circuit for determining the signal magnitude of the signal outputted from the first gain amplifier; and

a gain decision circuit for determining the gain to be applied in the variable gain amplifier based on the determined magnitude of the signal.

4. The readout circuit according to claim 1, wherein said first gain amplifier amplifies the signal to the maximum gain possible.

5. The readout circuit according to claim 2, wherein said signal, output from said analog-to-digital converter, is multiplied or divided based on the determined signal magnitude.

6. The readout circuit according to claim 1, wherein an offset is subtracted from the signal before the signal is processed by the first gain amplifier.

7. The readout circuit according to claim 6, wherein said offset is tunable.

8. The readout circuit according to claim 1, wherein an offset is subtracted from the signal after the signal is processed by the first gain amplifier.

9. The readout circuit according to claim 8, wherein said offset is tunable.

10. The readout circuit according to claim 1, wherein said pixel signal is single ended.

11. The readout circuit according to claim 1, wherein said pixel signal is differential.

12. An imager comprising:

an array of pixels;

a first amplifier amplifying a signal from said pixel array;

a signal level determining circuit for determining a gain factor based on a level of the amplified signal;

a variable gain amplifier, connected to said signal level determining circuit, for amplifying the signal from the first gain amplifier using the determined gain factor;

an analog-to-digital converter for digitizing an output of the second gain amplifier; and

a circuit for multiplying or dividing the signal from said analog-to-digital converter.

13. The imager according to claim 12, wherein an offset is subtracted from the signal before the signal is processed by the first gain amplifier.

14. The imager according to claim 13, wherein said offset is equal tunable.

15. The imager according to claim 12, wherein an offset is subtracted from the signal after the signal is processed by the first gain amplifier.

16. The imager according to claim 15, wherein said offset is tunable.

17. A pixel signal processing circuit comprising:

a pixel signal input;

a variable gain amplifier for amplifying the pixel signal depending on a signal level of the pixel signal; and

an analog-to-digital converter for digitizing the amplified signal.

18. The circuit according to claim 17, wherein said input signal is differential.

19. The circuit according to claim 17, wherein said input signal is single ended.

20. The circuit according to claim 17, further comprising a circuit for digitally multiplying or dividing the output of the analog-to-digital converter.

21. A method of increasing dynamic range of an imager, said method comprising:

amplifying a signal from a pixel in an imager pixel array;

determining the magnitude of the amplified pixel signal;

applying a gain to the pixel signal, wherein the gain is based on the determined signal magnitude; and

digitizing the pixel signal.

22. The method according to claim 21, further comprising the act of subtracting an offset from the signal prior to amplification.

23. The method according to claim 21, further comprising the act of subtracting an offset from the signal after amplification.

24. A method for increasing dynamic range, said method comprising:

subtracting an offset from a signal from a pixel in an imager pixel array;

amplifying said signal;

determining a magnitude of the amplified signal;

applying a gain to the pixel signal, wherein the gain is based on the signal magnitude

digitizing the signal; and

multiplying said digitized pixel signal.

25. A method of fabricating a pixel readout circuit comprising the acts of:

fabricating a first gain amplifier for amplifying a signal from a pixel array;

fabricating a signal level determining circuit for determining a gain factor based on a level of the amplified signal;

fabricating a variable gain amplifier, connected to said signal level determining circuit, for amplifying the signal from the first gain amplifier using the determined gain factor; and

fabricating an analog-to-digital converter for digitizing an output of the variable gain amplifier.