Solid-state imaging device

• US 20060214195A1
• Filed: 10/14/2005
• Published: 09/28/2006
• Est. Priority Date: 03/25/2005
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Kobayashi, Hiroshi, Inoue, Tadao, Yamamoto, Katsuyoshi, Mizuguchi, Toshitaka
• Granted Patent: US 8,013,370 B2
• Time in Patent Office: Days
• US Class Current: 257/222
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements

Abstract

A solid-state imaging device has a substrate in which are formed a pixel array portion having a plurality of pixels, and a peripheral circuitry portion. The device is characterized in that a first multilevel metallization structure is formed over the peripheral circuitry portion, and a second multilevel metallization structure thinner than the first multilevel metallization structure is formed over the pixel array portion.

Claims

1. A solid-state imaging device comprising:

a substrate in which are formed a pixel array portion having a plurality of pixels, and a peripheral circuitry portion peripheral to the pixel array portion;

a first multilevel metallization structure formed over the peripheral circuitry portion; and

a second multilevel metallization structure thinner than the first multilevel metallization structure formed over the pixel array portion.

2. The solid-state imaging device according to claim 1, wherein a single trench structure is formed over the pixel array portion by the first multilevel metallization structure over the peripheral circuitry portion and the second multilevel metallization structure over the pixel array portion, the trench structure has a protrusion in at least one corner thereof, and

the device further comprising a color filter film formed on a bottom of the trench structure by spin coating and a microlens over each pixel.

3. The solid-state imaging device according to claim 1, wherein a single trench structure is formed over the pixel array portion by the first multilevel metallization structure over the peripheral circuitry portion and the second multilevel metallization structure over the pixel array portion, the trench structure extends over a region that includes at least part of the pixel array portion.

4. The solid-state imaging device according to claim 3, wherein the trench structure region coincides with a central light-receiving pixel region of the pixel array portion that excludes peripheral black pixels.

5. The solid-state imaging device according to claim 3, wherein the trench structure region is wider than a central light-receiving pixel region of the pixel array portion that excludes peripheral black pixels.

6. The solid-state imaging device according to claim 1, wherein a single trench structure is formed over the pixel array portion by the first multilevel metallization structure over the peripheral circuitry portion and the second multilevel metallization structure over the pixel array portion, an optical color filter film is formed within the trench structure, a microlens for each pixel is formed over the optical color filter film, and the optical color filter film has a thickness which is substantially equal to the depth of the trench structure.

7. The solid-state imaging device according to claim 1, wherein a single trench structure is formed over the pixel array portion by the first multilevel metallization structure over the peripheral circuitry portion and the second multilevel metallization structure over the pixel array portion, an optical color filter film is formed within the trench structure, a microlens for each pixel is formed over the optical color filter film, and the optical color filter film has a thickness which is smaller than the depth of the trench structure.

8. A solid-state imaging device comprising:

a substrate in which are formed a pixel array portion having a plurality of pixels, and a periphery circuitry portion peripheral to the pixel array portion;

a first multilevel metallization structure which is formed over the peripheral circuitry portion and has a plurality of connection layers; and

a second multilevel metallization structure which is formed over the pixel array portion and has a smaller number of connection layers than the first multilevel metallization structure.

9. A solid-state imaging device comprising:

a substrate in which are formed a pixel array portion having a plurality of pixels, and a periphery circuitry portion peripheral to the pixel array portion;

a first multilevel metallization structure which is formed over the peripheral circuitry portion and has a plurality of connection layers; and

a second multilevel metallization structure which is formed over the pixel array portion and has a smaller number of connection layers than the first multilevel metallization structure, over which a color filter film is formed at a level corresponding to the uppermost level of the first multilevel metallization structure.

10. A method for fabricating a solid-state imaging device with a substrate in which are formed a pixel array portion having a plurality of pixels, and a periphery circuitry portion peripheral to the pixel array portion, the method comprising the steps of:

forming on a surface of the substrate a multilevel metallization structure which has, over the peripheral circuitry portion, a lower multilevel metallization, an upper multilevel metallization and interlayer dielectric layers for each, and which has, over the pixel array portion, the lower multilevel metallization and its interlayer dielectric layers and also the interlayer dielectric layers of the upper multilevel metallization;

removing the interlayer dielectric layers of the upper multilevel metallization formed over the pixel array portion; and

forming, on the lower multilevel metallization over the pixel array portion, optical color filters for the pixels.