Semiconductor device

• US 20060214275A1
• Filed: 03/20/2006
• Published: 09/28/2006
• Est. Priority Date: 03/22/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Miyazaki, Takashi
• Granted Patent: US 7,205,669 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]

Abstract

A semiconductor device that exhibits an enhanced inhibition to a generation of voids in an underfill resin for encapsulation supplied between a semiconductor chip and an electronic component, which are mutually coupled through bump electrodes. The semiconductor device includes a first semiconductor chip and a second semiconductor chip, wherein bumps-formed surface of the first semiconductor chip is opposed to bumps-formed surface of the electronic component. The semiconductor device includes insulating films that function as protective films respectively formed on an uppermost surface of the first semiconductor chip and on an uppermost surface of the electronic component. Openings for supplying an underfill resin between the first semiconductor chip and the second semiconductor chip are provided in the vicinity of the bumps-formed regions of at least one of the insulating films.

Claims

1. A semiconductor device, comprising a first semiconductor chip having bumps on a surface thereof and an electronic component having bumps on a surface thereof, bumps-formed surface of said first semiconductor chip being opposed to bumps-formed surface of said electronic component,

wherein said semiconductor device comprises protective films respectively formed on an uppermost surface of said first semiconductor chip and on an uppermost surface of said electronic component, and

wherein an opening for supplying an underfill resin between said first semiconductor chip and said electronic component is provided in vicinity of the bumps-formed region of at least one of said protective films.

2. The semiconductor device according to claim 1, wherein

said opening passes through said bumps-formed region and extends from one end to the other end of said semiconductor chip or said electronic component having said opening therein.

3. The semiconductor device according to claim 1, wherein said opening passes through said bumps-formed region and is provided to have a geometry that is larger than and covers a region corresponding to a region extending from one end to the other end of said semiconductor chip or said electronic component, which is the other one of said semiconductor chip or said electronic component having said opening therein.

4. The semiconductor device according to claim 1, wherein said electronic component is a second semiconductor chip, which is different from said first semiconductor chip.

5. The semiconductor device according to claim 1, wherein said electronic component is an interposer.

6. The semiconductor device according to claim 1, wherein said electronic component is a circuit board.

7. A semiconductor device, comprising:

a first semiconductor chip including a plurality of first bumps formed on a surface thereof; and

an electronic component including a plurality of second bumps formed on a surface thereof, said electronic component being arranged to be opposed to said first semiconductor chip, each of said first bumps of said first semiconductor chip being joined to corresponding one of said second bumps of said electronic component, which are opposed to said first bumps, respectively, and a gap between said first semiconductor chip and said electronic component being encapsulated with an underfill resin,

wherein a first bumps-formed region having plurality of said first bumps arranged thereon is formed partially on said surface of said first semiconductor chip and a second bumps-formed region having plurality of said second bumps arranged thereon is formed partially on said surface of said electronic component, and

wherein a protective film is formed on a portion of at least one of the surface of said first semiconductor chip and the surface of said electronic component except said first bumps-formed region and/or said second bumps-formed region.