Magneto-resistive memory cells and devices having asymmetrical contacts and methods of fabrication therefor

• US 20060215445A1
• Filed: 03/17/2006
• Published: 09/28/2006
• Est. Priority Date: 03/28/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, In-Gyu, Kim, Dong-Chul, Lee, Moon-Sook
• Granted Patent: US 7,639,521 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Claims

1. A memory cell comprising:

a plug-type first electrode in a substrate;

a magneto-resistive memory element disposed on the first electrode; and

a second electrode disposed on the magneto-resistive memory element opposite the first electrode, the second electrode having an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element.

2. The memory cell of claim 1, wherein the area of overlap of the first electrode is substantially circular and has a diameter less than a minimum dimension of the area of overlap of the second electrode.

3. The memory cell of claim 1, wherein the magneto-resistive memory element comprises a colossal magneto-resistive material.

4. The memory cell of claim 1, wherein the magneto-resistive memory element comprises an insulating material with a perovskite phase and/or a transition metal oxide.

5. The memory cell of claim 1, wherein the resistive memory element comprises a layer pattern having a minimum planar dimension that is less than a minimum planar dimension of the second electrode.

6. The memory cell of claim 1, wherein the first electrode is disposed in an insulating layer and an insulating spacer is disposed between the first electrode and the insulating layer.

7. The memory cell of claim 6, wherein the first electrode partially fills a contact hole in the insulating layer, and wherein the magneto-resistive memory element extends into the contact hole to contact the first electrode.

8. A memory device comprising:

a plurality of first electrode lines arranged in parallel on a substrate;

a plurality of second electrode lines arranged in parallel on the substrate transverse to the first electrode lines;

a plurality of electrode plugs electrically coupled to the first electrode lines, respective ones of the electrode plugs disposed between ones of the first and second electrode lines at respective intersections thereof; and

a plurality of magneto-resistive memory elements, a respective one of which has a first surface electrically coupled to a respective one of the electrode plugs and a second surface electrically coupled to a second electrode line, wherein the second surface has a greater area than the first surface.

9. The memory device of claim 8, wherein the magneto-resistive memory elements comprise a colossal magneto-resistive material.

10. The memory device of claim 8, wherein the magneto-resistive memory elements comprise an insulating material with a perovskite phase and/or a transition metal oxide.

11. The memory device of claim 8, wherein an area of overlap between an electrode plug and a magneto-resistive memory is smaller than an area of overlap between the magneto-resistive memory element and the second electrode line.

12. The memory device of claim 8, wherein a width of a magneto-resistive memory element is greater than a width of the second electrode line contacting the magneto-resistive memory element.

13. The memory device of claim 8, wherein the plurality of magneto-resistive memory elements comprises an array of individual patterns disposed between ones of the first and second electrode lines at respective intersections thereof.

14. The memory device of claim 8, wherein the plurality of magneto-resistive memory elements comprises a plurality of regions in a magneto-resistive material layer that overlaps multiple ones of the electrode plugs.

15. A memory device comprising:

respective pluralities of parallel electrode lines disposed on a substrate at respective levels, wherein pluralities of electrode lines on adjacent levels extend transverse to one another;

respective insulating layers between the pluralities of electrode lines of adjacent levels;

respective pluralities of magneto-resistive memory elements disposed between adjacent ones of the insulating layers and the pluralities of electrode lines; and

respective pluralities of electrode plugs penetrating respective ones of the insulating layers at intersections of the electrode lines and coupling the electrode lines to the magneto-resistive memory elements.

16. The memory device of claim 15, wherein the electrode plugs have a diameter smaller than a width of the electrode lines.

17. The memory device of claim 15, wherein the magneto-resistive memory elements comprise a colossal magneto-resistive material.

18. The memory device of claim 15, wherein the magneto-resistive memory elements comprise an insulating material with a perovskite phase and/or a transition metal oxide.

19. The memory device of claim 15, wherein the magneto-resistive memory elements comprise layer patterns having substantially the same shape as the electrode lines.

20. A method of fabricating a memory cell, the method comprising:

forming an insulating layer on a substrate;

forming a contact hole in the insulating layer;

forming a first electrode in the contact hole;

forming a magneto-resistive memory element on the first electrode; and

forming a second electrode on the magneto-resistive memory element.

21. The method of claim 20, wherein an area of overlap of the magneto-resistive memory element and the first electrode is less than an area of overlap of the magneto-resistive memory element and the second electrode.

22. The method of claim 20, wherein forming a second electrode on the magneto-resistive memory element comprises:

forming a conductive layer on the magneto-resistive memory element; and

patterning the conductive layer to form the second electrode.

23. The method of claim 22, wherein the magneto-resistive memory element thin film disposed below the conductive layer is patterned simultaneously with the conductive layer.

24. The method of claim 22, further comprising, prior to the forming of the first electrode plug, forming insulating spacers on sidewalls of the first contact hole.

25. The method of claim 22, further comprising forming a conductive line electrically connected to the first electrode and perpendicular to the second electrode, wherein the conductive line is formed prior to the formation of the insulating layer.

26. The method of claim 22, further comprising:

forming a second insulating layer on the second electrode;

patterning the second insulating layer to form a second contact hole exposing a portion of the second electrode;

forming a third electrode in the second contact hole;

forming a second magneto-resistive memory element on the third electrode; and

forming a fourth electrode on the second magneto-resistive memory element.