Automatic gain control circuit for infrared receiver

• US 20060216042A1
• Filed: 03/24/2005
• Published: 09/28/2006
• Est. Priority Date: 03/24/2005
• Status: Abandoned Application

• Current Assignee: Avago Technologies ECBU IP Singapore Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies ECBU IP Singapore Pte Limited (Broadcom, Inc.)
• Inventors: Xu, Lian Chun, Tai, Wai Keat, Asuncion, John Julius, Yeo, Kok Soon, Teo, Chee Keong
• Application Number:
  US11/089,835
• Publication Number:
  US 20060216042A1
• Time in Patent Office: Days
• US Class Current: 398/209
• CPC Class Codes: H03G 3/3084 in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 10/66 Non-coherent receivers, e.g. using direct detection

Abstract

An optical receiver includes a photodetector coupled to a gain section having a variable gain stage. The gain stage provides an output voltage signal. A digital automatic gain control circuit is coupled to the output voltage signal and provides a digital output value to at least the variable gain stage. The gain of the variable gain stage is set according to the digital output value.

Claims

1. An optical receiver comprising:

a photodetector;

a gain section including a variable gain stage providing an output voltage signal; and

a digital automatic gain control circuit coupled to the output voltage signal and providing a digital output value to at least the variable gain stage, a gain of the variable gain stage being set according to the digital output value.

2. The optical receiver of claim 1 wherein the gain section further includes a fixed gain stage.

3. The optical receiver of claim 2 wherein the fixed gain stage is selectively bypassed according to a second digital output value from the digital automatic gain controller.

4. The optical receiver of claim 3 wherein the gain section further comprises a switch controlled according to the second digital output value, the switch coupling an output of the fixed gain stage to an output of the gain section in a first state and coupling an input of the fixed gain stage to the output of the gain section in a second state.

5. The optical receiver of claim 1 wherein the variable gain stage includes a variable resistor coupling an output of the variable gain stage to an input of the variable gain stage.

6. The optical receiver of claim 5 wherein the variable resistor comprises a switched resistor network.

7. The optical receiver of claim 6 wherein the switched resistor network includes a fixed resistor and a plurality of selectively switchable resistors.

8. The optical receiver of claim 1 wherein the digital automatic gain control circuit includes a peak detector circuit configured to detect a peak value of the output voltage signal and to provide a peak detector output, and a bottom detector circuit configured to detect a bottom value of the output voltage signal and to provide a bottom detector output.

9. The optical receiver of claim 8 wherein the digital automatic gain control circuit further includes

a reference and comparator section having a first comparator comparing the bottom detector output to a first reference voltage and a second comparator comparing the bottom detector output to a second reference voltage, the first reference voltage and the second reference voltage each being set according to the peak detector output.

10. The optical receiver of claim 9 wherein the digital automatic gain control circuit further comprises

a latch circuit coupled to the first comparator and to the second comparator;

and

a counter coupled to the latch circuit and providing a plurality of digital output values.

11. The optical receiver of claim 10 wherein the counter comprises a four-bit shift register.

12. The optical receiver of claim 10 further comprising

a switched resistor network having a first switchable resistor and a second switchable resistor in a feedback path of the variable gain stage;

a first fixed gain stage; and

a second fixed gain stage, wherein a first of the plurality of digital output values switches the first switchable resistor into the feedback path, a second of the plurality of digital output values switches a second switchable resistor into the feedback path, a third of the plurality of the digital output values bypasses the first fixed gain stage, and a fourth of the plurality of the digital output values bypasses the second fixed gain stage.

13. The optical receiver of claim 10 further comprising a clock generation circuit generating a clock signal from the output voltage signal.

14. The optical receiver of claim 13 wherein the digital automatic gain control circuit further comprises a second clock generation circuit generating a second clock signal and a third clock signal from the clock signal, the bottom detector circuit being reset according to the second clock signal and the counter being clocked according to the third clock.

15. The optical receiver of claim 1 wherein the optical receiver is integrated in an infrared transceiver.

16. The optical receiver of claim 15 wherein the infrared transceiver is integrated on a silicon chip.

17. The optical receiver of claim 1 further comprising a time out reset circuit configured to set gain of the gain section to maximum gain after a selected period of time.

18. The optical receiver of claim 17 wherein the gain section is set to maximum gain after one of a time out reset signal and a power on reset signal.

19. The optical receiver of claim 10 further comprising a time out reset circuit including logic coupled to the plurality of digital output values.

20. The optical receiver of claim 19 wherein the time out reset circuit includes

a capacitor having a first terminal and a second terminal connected to a voltage reference,

a first switch disposed between the first terminal of the capacitor and the voltage reference controlled by an output of the logic,

a second switch disposed between the first terminal of the capacitor and the voltage reference controlled by a clock signal, and

a current supply configured to provide current to the first terminal.