Method for fabricating semiconductor device

• US 20060216878A1
• Filed: 06/30/2005
• Published: 09/28/2006
• Est. Priority Date: 03/25/2005
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Sang Don
• Application Number:
  US11/169,707
• Publication Number:
  US 20060216878A1
• Time in Patent Office: Days
• US Class Current: 438/152
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method for fabricating a semiconductor device is provided, the method including forming a SiGe epitaxial layer pattern and a first Si epitaxial layer pattern on a semiconductor substrate, forming a second Si epitaxial layer on the entire surface, etching the second Si epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region, removing the SiGe epitaxial layer pattern through a sidewall of the trench to form a space under the first Si epitaxial layer, forming a gap-filling insulating film to at least fill up the space and the trench, forming a gate oxide film on the second Si epitaxial layer, and depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.

Claims

1. A method for fabricating a semiconductor device, comprising the steps of:

(a) forming a SiGe epitaxial layer, a first Si epitaxial layer and an insulating film on a semiconductor substrate;

(b) etching a predetermined region of the insulating film, the first Si epitaxial layer and the SiGe epitaxial layer to expose the semiconductor substrate, wherein the predetermined region includes a storage node contact region and a portion of a gate region adjacent thereto;

(c) removing the insulating film;

(d) forming a second Si epitaxial layer on the entire surface including the exposed semiconductor substrate;

(e) etching the second Si epitaxial layer, the first Si epitaxial layer, the SiGe epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region;

(f) removing the SiGe epitaxial layer through a sidewall of the trench to form a space under the first Si epitaxial layer;

(g) forming a gap-filling insulating film to at least fill up the space and the trench;

(h) forming a gate oxide film on the second Si epitaxial layer; and

(i) depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.

2. The method according to claim 1, wherein the step (b) comprises:

forming a photoresist film on the entire surface of the semiconductor substrate;

forming a photoresist film pattern exposing the predetermined region by exposing and developing the photoresist film, wherein the portion of the gate region of the predetermined region has a line width of M; and

etching the insulating film, the Si epitaxial layer and the SiGe epitaxial layer using the photoresist film pattern as an etching mask.

3. The method according to claim 2, wherein the M ranges from ⅓

F to F, wherein F is a gate line width.

4. The method according to claim 1, wherein the insulating film comprises an oxide film.

5. The method according to claim 1, wherein the insulating film comprises a stacked structure of an oxide film and a nitride film.

6. The method according to claim 1, wherein the removal process for the insulating film in the step (e) is performed via a wet etching method.

7. The method according to claim 1, wherein a thickness of the second Si epitaxial layer ranges from 10 to 100 nm.

8. The method according to claim 1, wherein the removal process for the SiGe epitaxial layer in the step (f) is performed via one method selected from the group consisting of a wet etching method utilizing a mixed etchant containing HF, H₂O₂ and CH₃COOH, a plasma etching method utilizing a mixed gas containing (CF₄ or CH₂F₂), N₂ and O₂, and combinations thereof.

9. The method according to claim 8, wherein a volume ratio of HF, H₂O₂ and CH₃COOH in the mixed etchant is 1:

2;

3.

10. The method according to claim 1, wherein the step (g) comprises:

forming a thermal oxide film filling up the space; and

forming an oxide film for a device isolation film to fill up the trench.

11. The method according to claim 10, further comprising

forming a nitride film at the interface of the thermal oxide film and the oxide film for the device isolation film.

12. The method according to claim 1, wherein the step (g) comprises:

forming a thermal oxide film to fill a portion of the space;

forming a nitride film to fill up a remaining portion of the space; and

forming an oxide film for the device isolation film to fill up the trench.