Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same

• US 20060216897A1
• Filed: 12/16/2005
• Published: 09/28/2006
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sungyoung, Shin, Dongsuk
• Granted Patent: US 7,642,578 B2
• Time in Patent Office: Days
• US Class Current: 438/282
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

Claims

1. A method of fabricating a field effect transistor (FET), comprising:

forming source and drain regions on a semiconductor substrate;

forming a plurality of preliminary channel regions coupled between the source and drain regions;

etching the preliminary channel regions; and

annealing the etched preliminary channel regions to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

2. The method of claim 1, wherein the preliminary channel regions have a substantially rectangular cross-sectional shape.

3. The method of claim 1, wherein the preliminary channel regions have corners in cross-section.

4. The method of claim 1, -wherein the etching is performed in an atmosphere containing HCl.

5. The method of claim 1, wherein the etching is performed in an atmosphere containing H₂.

6. The method of claim 1, wherein the etching is performed in an atmosphere containing HCl and H₂.

7. The method of claim 6, wherein a ratio of a flow rate of HCl to a flow rate of H₂ is from 3:

7 to 1;

1.

8. The method of claim 6, wherein the ratio of flow rate of HCl to flow rate of H₂ is 3:

5.

9. The method of claim 1, wherein the etching is performed at a temperature of 600 to 900 degrees C.

10. The method of claim 1, wherein the etching is performed for a period of 1 to 120 seconds.

11. The method of claim 1, wherein the etching is performed at a pressure of 10 to 100 Torr.

12. The method of claim 1, wherein the annealing is performed in an atmosphere containing H₂.

13. The method of claim 1, wherein the annealing is performed with H₂ introduced at a flow rate of 1 to 500 sccm.

14. The method of claim 1, wherein the annealing is performed at a temperature of 600 to 900 degrees C.

15. The method of claim 1, wherein the annealing is performed for a period of 10 to 800 seconds.

16. The method of claim 1, further comprising, after forming the preliminary channel regions, cleaning the structure to remove oxide from the structure.

17. The method of claim 16, wherein the cleaning is performed in an atmosphere containing at least one of H₂, Ar and He.

18. The method of claim 16, wherein the cleaning is performed at a temperature of 600 to 900 degrees C.

19. The method of claim 16, wherein the cleaning is performed at a gas flow rate of 1 to 500 sccm.

20. The method of claim 16, wherein the cleaning is performed for a period of 1 to 5 minutes.

21. The method of claim 16, wherein the cleaning is performed at a pressure of 0.1 to 10 Torr.

22. The method of claim 1, wherein forming the plurality of preliminary channel regions comprises forming a channel layer and a sacrificial layer vertically adjacent to the channel layer.

23. The method of claim 22, wherein the channel layer and the sacrificial layer are formed epitaxially.

24. The method of claim 22, wherein the channel layer is a silicon layer.

25. The method of claim 22, wherein the sacrificial layer is a SiGe layer.

26. The method of claim 22, wherein forming the plurality of preliminary channel regions further comprises trimming the channel layer to a desired dimension such that a front surface of at least one of the preliminary channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions.

27. The method of claim 26, wherein the trimming comprises etching the channel layer.

28. The method of claim 27, wherein etching the channel layer comprises a chemical dry etch.

29. The method of claim 22, wherein forming the plurality of preliminary channel regions further comprises forming a mask layer over the channel layer and sacrificial layer, the mask layer defining a region separating the FET channel regions.

30. The method of claim 1, wherein forming the plurality of preliminary channel regions comprises forming a plurality of sacrificial layers vertically adjacent to a channel layer.

31. The method of claim 30, wherein the sacrificial layers comprise SiGe.

32. The method of claim 31, wherein an upper sacrificial layer has a lower concentration of germanium than a lower sacrificial layer.

33. The method of claim 1, further comprising purging a process chamber between etching the preliminary channel regions and annealing the etched preliminary channel regions.

34. The method of claim 1, wherein the etching and annealing steps are performed at least two times.

35. The method of claim 34, further comprising purging steps between a prior etching step and a next annealing step.

36. The method of claim 1, further comprising forming a gate dielectric layer on the FET channel regions.

37. The method of claim 1, further comprising forming a gate surrounding the FET channel regions.

38. The method of claim 37, wherein the gate comprises polysilicon.

39. The method of claim 37, wherein the gate comprises metal.

40. A method of fabricating a field effect transistor (FET), comprising:

alternately stacking at least one channel layer and at least one sacrificial layer on a substrate;

forming source and drain regions on the substrate coupled to the alternately stacked at least one channel layer and at least one sacrificial layer;

patterning the alternately stacked at least one channel layer and at least one sacrificial layer to form a plurality of preliminary channel regions coupled between the source and drain regions;

removing a remaining portion of the at least one sacrificial layer;

etching the preliminary channel regions; and

annealing the etched preliminary channel regions to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

41. The method of claim 40, wherein the preliminary channel regions have a substantially rectangular cross-sectional shape.

42. The method of claim 40, wherein the preliminary channel regions have corners in cross-section.

43. The method of claim 40, wherein the at least one channel layer and the at least one sacrificial layer are formed epitaxially.

44. The method of claim 40, wherein the at least one channel layer is a silicon layer.

45. The method of claim 40, wherein the at least one sacrificial layer is a SiGe layer.

46. The method of claim 40, wherein forming the plurality of preliminary channel regions further comprises trimming the at least one channel layer to a desired dimension such that a front surface of at least one of the preliminary channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions.

47. The method of claim 46, wherein the trimming comprises etching the at least one channel layer.

48. The method of claim 47, wherein etching the at least one channel layer comprises a chemical dry etch.

49. The method of claim 40, wherein forming the plurality of preliminary channel regions further comprises forming a mask layer over the at least one channel layer and at least one sacrificial layer, the mask layer defining a region separating the FET channel regions.

50. The method of claim 40, wherein forming the plurality of preliminary channel regions comprise forming a plurality of sacrificial layers vertically adjacent to the channel layer.

51. The method of claim 50, wherein the sacrificial layers comprise SiGe.

52. The method of claim 51, wherein an upper sacrificial layer has a lower concentration of germanium than a lower sacrificial layer.

53. The method of claim 40, further comprising purging a process chamber between etching the preliminary channel regions and annealing the etched preliminary channel regions.

54. The method of claim 40, further comprising forming a gate dielectric layer on the FET channel regions.

55. The method of claim 40, further comprising forming a gate surrounding the FET channel regions.

56. The method of claim 55, wherein the gate comprises polysilicon.

57. The method of claim 55, wherein the gate comprises metal.

58. A method of fabricating a field effect transistor (FET), comprising:

forming source and drain regions on a semiconductor substrate;

forming a plurality of preliminary channel regions coupled between the source and drain regions, said forming a plurality of preliminary channel regions comprising;

(i) forming a channel layer and a sacrificial layer vertically adjacent to the channel layer, and. (ii) trimming the channel layer to a desired dimension such that a front surface of at least one of the preliminary channel regions is offset normal to the front surface of the source and drain regions;

etching the preliminary channel regions; and

annealing the etched preliminary channel regions to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

59. The method of claim 58, wherein the preliminary channel regions have a substantially rectangular cross-sectional shape.

60. The method of claim 58, wherein the preliminary channel regions have corners in cross-section.

61. The method of claim 58, further comprising, after forming the preliminary channel regions, cleaning the structure to remove oxide from the structure.

62. The method of claim 58, wherein the channel layer and the sacrificial layer are formed epitaxially.

63. The method of claim 58, wherein the channel layer is a silicon layer.

64. The method of claim 58, wherein the sacrificial layer is a SiGe layer.

65. The method of claim 58, wherein the trimming comprises etching the channel layer.

66. The method of claim 65, wherein etching the channel layer comprises a chemical dry etch.

67. The method of claim 58, wherein forming the plurality of preliminary channel regions comprises forming a plurality of sacrificial layers vertically adjacent to the channel layer.

68. The method of claim 67, wherein the sacrificial layers comprise SiGe.

69. The method of claim 68, wherein an upper sacrificial layer has a lower concentration of germanium than a lower sacrificial layer.

70. The method of claim 58, further comprising purging a process chamber between etching the preliminary channel regions and annealing the etched preliminary channel regions.

71. The method of claim 58, further comprising forming a gate dielectric layer on the FET channel regions.

72. The method of claim 58, further comprising forming a gate surrounding the FET channel regions.

73. The method of claim 72, wherein the gate comprises polysilicon.

74. The method of claim 72, wherein the gate comprises metal.

75. A method of fabricating a field effect transistor (FET), comprising:

forming source and drain regions on a semiconductor substrate;

forming a preliminary channel region coupled between the source and drain regions, said forming a preliminary channel region comprising;

(i) forming a channel layer and a sacrificial layer vertically adjacent to the channel layer, and (ii) trimming the channel layer to a desired dimension such that a front surface of the preliminary channel region is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions;

removing a remaining portion of the sacrificial layer;

etching the trimmed channel layer; and

annealing the etched channel layer to form a FET channel region, the FET channel region having a substantially circular cross-sectional shape.

76. A method of fabricating a field effect transistor (FET), comprising:

forming source and drain regions on a semiconductor substrate;

forming a preliminary channel region coupled between the source and drain regions, said forming a preliminary channel region comprising forming a channel layer and a sacrificial layer vertically adjacent to the channel layer;

removing a remaining portion of the sacrificial layer;

etching the preliminary channel region; and

annealing the etched preliminary channel region to form a FET channel region, the FET channel region having a substantially circular cross-sectional shape.

77. A method of fabricating a field effect transistor (FET), comprising:

forming source and drain regions on a semiconductor substrate;

forming a plurality of preliminary channel regions coupled between the source and drain regions;

etching the preliminary channel regions; and

annealing the etched preliminary channel regions to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

78. A field effect transistor (FET), comprising:

a semiconductor substrate;

source and drain regions on the semiconductor substrate;

a plurality of FET channel regions coupled between the source and drain regions, the FET channel regions having a substantially circular cross-sectional shape, the FET channel regions being trimmed to a desired dimension such that a front surface of at least one of the FET channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions.

79. The field effect transistor of claim 78, further comprising a gate dielectric layer on the FET channel regions.

80. The field effect transistor of claim 78, further comprising a gate surrounding the FET channel regions.

81. The field effect transistor of claim 78, wherein the gate comprises polysilicon.

82. The field effect transistor of claim 78, wherein the gate comprises metal.

83. A field effect transistor (FET), comprising:

a semiconductor substrate;

source and drain regions on the semiconductor substrate;

a FET channel region coupled between the source and drain regions, the FET channel region having a substantially circular cross-sectional shape, the FET channel region being trimmed to a desired dimension such that a front surface of the FET channel region is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions.