Plasma pre-treating surfaces for atomic layer deposition

• US 20060216932A1
• Filed: 02/21/2006
• Published: 09/28/2006
• Est. Priority Date: 02/22/2005
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM America Incorporated (ASM International NV)
• Inventors: Goundar, Kamal Kishore, Kemeling, Nathanael R.C., Sprey, Hessel, Fukuda, Hideaki, Kumar, Devendra, Stokhof, Maarten
• Granted Patent: US 7,498,242 B2
• Time in Patent Office: Days
• US Class Current: 438/641
• CPC Class Codes: C23C 14/02 Pretreatment of the material to be coated C23C14/04 takes precedence
• CPC Class Codes: C23C 16/02 Pretreatment of the material to be coated C23C16/04 takes precedence
• CPC Class Codes: C23C 16/36 Carbonitrides
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76873 for electroplating

Abstract

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed in, preferably, insulating layers. The layers are then adequately treated with a particular plasma process. Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction can occur without significantly filling the pores forming improved interconnects.

Claims

1. A metallization process, comprising:

forming trenches in a desired interconnect pattern in a low k insulating layer above a semiconductor substrate;

treating an exposed surface of the trenches with a plasma process under conditions sufficient to improve a barrier property of a barrier layer compared to a barrier layer associated with a surface of trenches that have not undergone the plasma process; and

after treating an exposed surface of the trenches with the plasma process, lining the surfaces of the trenches with the barrier layer by an atomic layer deposition (ALD) process.

2. The process of claim 1, further comprising depositing a copper seed layer over the barrier layer.

3. The process of claim 1, further comprising forming vias in the low k insulating layer in communication with the trenches.

4. The process of claim 1, wherein the plasma process is a He/H₂ plasma process.

5. The process of claim 4, wherein between the formation of the trenches and the plasma processing, the trenches are not subject to oxidation.

6. The process of claim 4, further comprising further treating an exposed part of an underlying conductive element with an oxide removal process to reduce any oxidized metal, wherein said oxide removal process occurs before the He/H₂ plasma process.

7. The process of claim 1, wherein the plasma process is a He/H₂ plasma process, and wherein the He/H₂ plasma process reduces oxide from an underlying conductive element while treating trench sidewalls to improve the barrier property.

8. The process of claim 1, wherein the improved barrier property is an extended lifetime of more than 10 years of use with less than a 0.1% cumulative failure risk for a circuit formed by the process.

9. The process of claim 8, wherein the extended lifetime is about 17 years.

10. The process of claim 1, wherein the plasma process involves a He/H₂ plasma treatment at 250-350°

C.

11. The process of claim 1, wherein the interconnect pattern comprises vias exposing conductors at the bottom thereof, and the improved barrier property is a lower via chain resistance than a via that has not had the plasma treatment.

12. The process of claim 11, wherein the lower via chain resistance is between about 1% and about 20% lower than a resistance in a via in a trench from a process that is identical except for the absence of the He/H₂ plasma treatment.

13. The process of claim 1, wherein the improved barrier property is a more uniform resistance of the barrier layer.

14. The process of claim 1, wherein the improved barrier property is an improved failure time in electro-migration.

15. The process of claim 1, wherein the conditions sufficient to improve the barrier property comprise an amount of time of exposure, wherein said exposed surface is treated for 5 to 20 seconds.

16. The process of claim 1, wherein the conditions sufficient to improve the barrier property comprise a plasma generated at 100-200 W at 13.5 MHz.

17. The process of claim 1, wherein the conditions sufficient to improve the barrier property comprise a plasma comprising 190 to 40 parts He to 10 to 160 parts H₂.

18. The process of claim 1, wherein the barrier layer comprises tungsten, nitrogen, and carbon.

19. The process of claim 18, wherein the barrier layer is deposited so that it is approximately 35 to 45 angstroms thick.

20. The process of claim 18, wherein the barrier layer consists essentially of WN_xC_y.

21. The process of claim 20, further comprising depositing a copper seed layer on the barrier layer by a physical vapor deposition (PVD) process.

22. The process of claim 1, wherein the insulating layer comprises a low-k siloxane polymer.

23. The process of claim 1, wherein the plasma process comprises supplying plasma products to the exposed surface of the trenches, wherein the plasma products are generated remotely.

24. The process of claim 1, wherein 30 to 60 ALD cycles are performed in establishing an effective barrier layer.

25. The process of claim 1, wherein the exposed surface of the trenches does not comprise an etch stop or CMP stop layer.

26. The process of claim 1, further comprising forming a via in the insulating layer, wherein said trenches and vias are formed by a via first, trench later (VFTL) process.

27. The process of claim 1, wherein said low k insulating layer comprises a buried etch stop layer.

28. An integrated circuit comprising:

a trench in a desired wiring pattern in an insulating layer above a semiconductor substrate;

a contact via extending downwardly from a floor of the trench to expose at least part of an underlying conductive element;

a barrier layer directly on a surface of the trench, wherein said barrier layer comprises tungsten, nitrogen and carbon; and

a copper layer attached to said barrier layer.

29. The circuit of claim 28, wherein the circuit has a 0.1% cumulative failure risk of more than 10 years at a use condition of 110°

C. and 5.5*10⁵ A/cm² current density.

30. The circuit of claim 28, wherein the insulating layer comprises a low-k material.

31. The circuit of claim 30, wherein the low k material is selected from the group consisting of:

a low-k material, an ultra-low k material, an extreme low k material, and a siloxane polymer insulation film.

32. The circuit of claim 31, wherein the low k material is porous and has a dielectric of less than about 3.3.

33. The circuit of claim 31, wherein the low k material has —

SiR₂O—

repeating structural units.

34. The circuit of claim 28, wherein a standard deviation of the thickness of the barrier layer is about 1%.

35. The circuit of claim 34, wherein the barrier layer is about 20-60 angstroms thick.

36. The circuit of claim 28, wherein said barrier layer has greater than about 95% step coverage.

37. The circuit of claim 28, wherein the insulating layer is a silicon-containing hydrocarbon compound of the general formula Si_α

O_β

C_xH_y (where α

, β

, x, and y are integers).

38. A cluster tool configured for metallization, comprising:

a first chamber that is configured for in situ plasma treatment of an insulating surface on a substrate;

a second chamber that is configured for an atomic layer deposition of a metal nitride carbide barrier material;

a third chamber that is configured for applying a seed layer to the metal nitride carbide material; and

a volume between said first, second, and third chambers, said volume allowing the substrate to travel between the first, second, and third chambers within said volume, and wherein said volume between said first, second, and third chambers is configured to maintain vacuum during transfer among the chambers.

39. The cluster tool of claim 38, further comprising a source of copper operatively connected to the third chamber.

40. The cluster tool of claim 38, further comprising a source of nitrogen and a source of carbon operatively connected to said second chamber.

41. The cluster tool of claim 40, further comprising a source of metal operatively connected to said second chamber.

42. The cluster tool of claim 41, wherein the source of metal comprises tungsten.

43. A method of making an integrated circuit comprising:

plasma processing a surface of an insulating layer, wherein said plasma processing comprises the use of a reducing plasma to process the surface; and

after plasma processing the surface of the layer, lining said surface with a barrier layer deposited via atomic layer deposition (ALD), wherein the barrier layer comprises metal, carbon, and nitrogen, and wherein an interface between the surface and the barrier layer is relatively uniform in that the standard deviation of thickness of the barrier layer is less than about 5% of the mean of the thickness of the barrier.

44. The method of claim 43, further comprising forming an electrochemical deposition seed layer over the barrier layer.

45. The method of claim 43, wherein said metal is tungsten.

46. The method of claim 43, wherein said reducing plasma comprises a plasma formed from H₂ and He.

47. The method of claim 46, wherein the plasma comprises 190 to 40 parts He to 10 to 160 parts H₂.

48. The method of claim 43, wherein the layer that comprises the surface that is to be processed by the plasma comprises a low k insulating material.

49. The method of claim 43, wherein said insulating material is selected from the group consisting of at least one of:

fluorinated silicate glass, tetraethylorthosilicate, and a porous insulating material.

50. The method of claim 43, wherein the standard deviation of thickness of the barrier layer is less than about 1% of the mean of the thickness of the barrier.

51. The method of claim 44, wherein the surface that is plasma processed is a surface of a via and a surface of a trench.

52. The method of claim 45, wherein the surface that is plasma processed is a surface of a damascene trench.

53. The method of claim 52, wherein the circuit has an extended lifetime of more than 10 years of use with less than 0.1% cumulative failure risk.

54. The method of claim 43, wherein said plasma processing is performed sufficiently so that a circuit that is made with the plasma processing has a superior barrier property than a circuit that is made without the plasma processing, wherein the circuits are otherwise made by a same process.

55. The method of claim 43, wherein said plasma processing is performed sufficiently so that a circuit that is made with the plasma processing has a lower resistance than a circuit that is made without the plasma processing, wherein the circuits are otherwise made by a same process.

56. A metallization process, comprising:

forming trenches and vias in a desired interconnect pattern in a low k insulating layer above a semiconductor substrate;

treating an exposed surface of the trench with a plasma process, wherein said plasma process comprises a H₂/He plasma, and wherein said plasma process can treat substantially all of the exposed surfaces of the trenches; and

after treating an exposed surface of the trench with the plasma process, lining the surfaces of the trench with the liner layer by an atomic layer deposition (ALD) process.

57. The metallization process of claim 56, wherein the liner layer is a barrier layer.

58. The metallization process of claim 57, wherein the barrier layer comprises metal, carbon, and nitrogen.

59. The metallization process of claim 58, wherein the metal comprises tungsten.

60. The metallization process of claim 59, wherein the plasma process is generated remotely.

61. The metallization process of claim 60, wherein the plasma process is an unbiased plasma process.