Equalizing device and method capable of WLAN applications

• US 20060217069A1
• Filed: 03/24/2005
• Published: 09/28/2006
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chen, Wei-Hong, Peng, Wei-Chung, Lin, Huashih
• Granted Patent: US 7,496,341 B2
• Time in Patent Office: Days
• US Class Current: 455/63.100
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A communication system may include an equalizing device for DC-offset mitigation. The system includes: an input analog-to-digital converter configured to receive an input signal and produce a digital signal from the input signal; and a DC-offset estimation device coupled with the input analog-to-digital converter. The DC-offset estimation device is configured to produce a quantized DC-offset estimate from the digital signal. And the input analog-to-digital converter is configured to receive the quantized DC-offset estimate and to adjust a DC offset of the digital signal.

Claims

1. A communication system capable of conducting DC-offset mitigation, the system comprising:

an input analog-to-digital converter configured to receive an input signal and produce a digital signal from the input signal; and

a DC-offset estimation device coupled with the input analog-to-digital converter, the DC-offset estimation device being configured to produce a quantized DC-offset estimate from the digital signal,

wherein the input analog-to-digital converter is configured to receive the quantized DC-offset estimate and to adjust a DC offset of the digital signal.

2. The communication system of claim 1, wherein the DC-offset estimation device estimates the DC offset from the digital signal during a transmission of a short training symbol provided by the digital signal.

3. The communication system of claim 1, wherein the input analog-to-digital converter is a pipeline analog-to-digital converter comprising a plurality of analog-to-digital converter stages connected in a pipeline.

4. The communication system of claim 3, wherein an analog-to-digital converter stage comprises:

a sample-and-hold circuit configured to receive the input signal and to produce a sampled output;

a gain amplifier coupled to the sample-and-hold circuit and configured to amplify the sampled output to produce an amplified output;

a first analog-to-digital converter coupled to the sample-and-hold circuit and configured to produce a first digital output;

a first digital-to-analog converter coupled to the first analog-to-digital converter and configured to produce a first analog output; and

a summing node coupled to the gain amplifier and the first digital-to-analog converter, the summing node being configured to receive an analog DC-offset estimate and to subtract the first analog output and the analog DC-offset estimate from the amplified output to produce an adjusted output.

5. The communication system of claim 4, wherein the analog-to-digital converter stage further comprises a second digital-to-analog converter coupled to the DC-offset estimation device and the summing node and configured to produce the analog DC-offset estimate from the quantized DC-offset estimate.

6. The communication system of claim 5, wherein the second digital-to-analog converter comprises a switched-capacitor digital-to-analog converter.

7. The communication system of claim 4, wherein the DC-offset estimation device is configured to provide the analog-to-digital converter stage a control signal configured to select a reference voltage level for a DC-offset adjustment at the analog-to-digital converter stage.

8. The communication system of claim 4, wherein the first digital output is provided as a digital signal, and the adjusted output is provided as an analog residual signal.

9. A WLAN direct conversion device capable of conducting DC-offset mitigation, the device comprising:

a base-band receiver;

a local oscillator;

a first signal-processing branch being coupled to an input, to the local oscillator, and to the base-band receiver;

a second signal-processing branch being coupled to the input, to the local oscillator through a 90-degree phase shifter, and to the base-band receiver;

a first DC-offset estimation circuit coupled to the first branch and the base-band receiver; and

a second DC-offset estimation circuit coupled to the first branch and the base-band receiver.

10. The device of claim 9, wherein each of the first and second branches further comprises:

a mixer, coupled to the local oscillator;

a filter coupled to the mixer;

a variable gain amplifier coupled to the filter; and

an analog-to-digital converter coupled to the variable gain amplifier and the base-band receiver.

11. The device of claim 10, wherein the first DC-offset estimation circuit receives an output signal from the analog-to-digital converter of the first branch and is configured to provide a digital offset code to the analog-to-digital converter of the first branch.

12. The device of claim 10, wherein the second DC-offset estimation circuit receives an output signal from the analog-to-digital converter of the second branch and is configured to provide a digital offset code to the analog-to-digital converter of the second branch.

13. The device of claim 10, wherein at least one of the first and second DC-offset estimation circuits is configured to provide a residual analog offset signal to the base-band receiver.

14. The device of claim 10, further comprising a subtractor for digitally canceling a residual DC offset.

15. The device of claim 10, wherein at least one of the analog-to-digital converters of the first and second branches comprises a plurality of pipelined analog-to-digital converters.

16. A DC-offset mitigation method for a communication system, the method comprising:

receiving an input signal;

estimating a DC offset of the analog input signal;

quantizing the estimated DC offset to produce a quantized DC-offset estimate; and

producing from the input signal an adjusted digital signal, the adjusted digital signal having been adjusted with a DC-offset level approximating the quantized DC-offset estimate.

17. The method of claim 16, further comprises:

producing DC-offset control signals for a plurality of analog-to-digital converter (ADC) stages;

selecting DC-offset voltages for subtractions at the plurality of analog-to-digital converter (ADC) stages; and

adjusting the input range at each of the plurality of analog-to-digital converter (ADC) stages to mitigate the DC offset.

18. The method of claim 17, wherein the estimating of the DC offset comprises computing an average of the analog-to-digital converter stages.

19. The method of claim 17, wherein selecting the DC-offset voltages further comprises:

encoding the DC offset into a digital binary code; and

separating the digital binary offset code into partial DC offset codes for the ADC stages.

20. The method in claim 17, wherein adjusting the input range comprises:

applying a DC offset code to an analog-to-digital converter stage;

selecting a correction voltage from a plurality of reference voltages;

dividing the correction voltage by a predetermined factor; and

subtracting the divided correction voltage from an input signal of the analog-to-digital converter stage.