VOLTAGE FAULT DETECTION AND PROTECTION

• US 20060217906A1
• Filed: 12/19/2005
• Published: 09/28/2006
• Est. Priority Date: 03/22/2005
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Barbara, Bruce J.
• Granted Patent: US 7,609,080 B2
• Time in Patent Office: Days
• US Class Current: 702/60
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

A fault detection and protection circuit can include a comparing circuit (e.g., a comparator or a detector) that can be connected to a power line supplying power to an electronic device being tested. The comparing circuit can be configured to detect a fault in which the power line is shorted to ground. For example, the electronic device being tested may have a fault in which its power terminals are shorted to ground. Upon detection of such a fault, the comparing circuit activates one or more switches that shunt capacitors or other energy storage devices on the power line to ground. The comparing circuit may alternatively or in addition activate one or more switches that disconnect the power supply supplying power to the electronic device under test from probes contacting the electronic device.

Claims

1. A method of detecting and responding to a fault in a semiconductor device under test, the method comprising:

monitoring at least one electrical characteristic of a power line electrically connected to the semiconductor device under test for indications of the fault;

determining from the at least one electrical characteristic whether a fault condition exists; and

in response to determining the fault condition exists, diverting power from a probe in electrical connection with a terminal of the semiconductor device under test affected by the fault, wherein the diverting occurs in close proximity to the probe in relation to a power supply supplying power to the power line.

2. The method of claim 1 further comprising providing a capacitor electrically connected to the power line.

3. The method of claim 2, wherein the diverting comprises at least one of disconnecting the probe from the capacitor, disconnecting the probe from the power supply, or connecting the probe to ground.

4. The method of claim 3, wherein the diverting comprises

disconnecting the probe from the capacitor.

5. The method of claim 3, wherein the diverting comprises disconnecting the probe from the power supply.

6. The method of claim 3, wherein the diverting comprises disconnecting the probe from the capacitor and disconnecting the probe from the power supply.

7. The method of claim 3, wherein the diverting comprises connecting the probe to ground.

8. The method of claim 3, wherein:

the probe is one of a plurality of probes of a probe card assembly configured to contact a plurality of terminals of the semiconductor device, and

the monitoring comprises monitoring a portion of the power line disposed on the probe card assembly.

9. The method of claim 8, wherein the determining comprises comparing a voltage on the power line to a reference voltage.

10. The method of claim 9, wherein the fault is a short to ground.

11. The method of claim 1 further comprising testing the electronic device.

12. The method of claim 1, wherein the monitoring comprising monitoring a voltage on the power line.

13. The method of claim 1, wherein the power supply is connected to a first end of the power line and the probe is connected to a second end of the power line, and the monitoring comprises monitoring a voltage on the power line at a location on the power line that is in close proximity to the probe relative to the power supply.

14. The method of claim 1, wherein the monitoring comprises monitoring the at least one electrical characteristic at a plurality of locations on a power plane, wherein the power plane is electrically connected through the power line to a power supply, and a plurality of probes are electrically connected to the power plane and disposed to contact a plurality of terminals of a plurality of electronic devices.

15. The method of claim 14, wherein the monitoring further comprises determining whether a difference in voltages between at least one pair of locations on the power plane exceeds a predetermined threshold.

16. An electronic apparatus comprising:

an electrically conductive line;

a probe electrically connected to the line and configured to contact a power terminal of an electronic device;

detecting means for detecting a fault at the power terminal; and

protecting means for protecting the probe from a fault detected by the detecting means.

17. The apparatus of claim 16 further comprising a capacitor electrically connected to the line.

18. The apparatus of claim 17, wherein the protecting means protects the probe from a fault by at least one of disconnecting the probe from the capacitor, disconnecting the probe from a power supply connected to the line, or connecting the probe to ground.

19. The apparatus of claim 18, wherein the protecting means protects the probe from a fault by disconnecting the probe from the capacitor.

20. The apparatus of claim 18, wherein the protecting means protects the probe from a fault by disconnecting the probe from the power supply.

21. The apparatus of claim 18, wherein the protecting means protects the probe from a fault by disconnecting the probe from the capacitor and disconnecting the probe from the power supply.

22. The apparatus of claim 18, wherein the protecting means protects the probe from a fault by connecting the probe to ground.

23. The apparatus of claim 18 further comprising a probe card assembly comprising a plurality of probes configured to contact a plurality of terminals of the electronic device, wherein the conductive line and the detecting means are disposed on the probe card assembly.

24. The apparatus of claim 23, wherein the protecting means is disposed on the probe card assembly.

25. The apparatus of claim 23, wherein:

the probe card assembly comprises a probe substrate to which the probes are attached, and

the detecting means is disposed on the probe substrate.

26. The apparatus of claim 25, wherein the protecting means is disposed on the probe substrate.

27. The apparatus of claim 23, wherein the detecting means compares a voltage on the line to a reference voltage.

28. The apparatus of claim 27, wherein the reference voltage corresponds to a short to ground at the power terminal.

29. The apparatus of claim 16 further comprising:

a power plane electrically connected to the electrically conductive line; and

a plurality of probes electrically connected to the line through the power plane and configured to contact power terminals of a plurality of electronic devices,

wherein the detecting means monitors the plane to detect a fault at one of the power terminals.

30. The apparatus of claim 29, wherein the detecting means compares voltages sampled from a plurality of points on the power plane.

31. An electronic apparatus comprising:

an electrically conductive line;

a probe electrically connected to the line and configured to contact a power terminal of an electronic device;

a capacitor electrically connected to the line;

a comparing circuit configured to compare a voltage on the line to a reference voltage; and

a switch activated by an output of the comparing circuit and configured to at least one of disconnect the probe from the capacitor, disconnect the probe from a power supply supplying power to the line, or connect the probe to ground.

32. The apparatus of claim 31 further comprising a probe card assembly comprising a plurality of probes configured to contact a plurality of terminals of the electronic device, wherein the conductive line and the comparing circuit are disposed on the probe card assembly.

33. The apparatus of claim 32, wherein the switch is disposed on the probe card assembly.

34. The apparatus of claim 32, wherein:

the probe card assembly comprises a probe substrate to which the probes are attached, and

the comparing circuit is disposed on the probe substrate.

35. The apparatus of claim 34 wherein the switch is disposed on the probe substrate.

36. A method of detecting and responding to a fault in a semiconductor device under test, the method comprising:

monitoring at least one electrical characteristic of a power line electrically connected to the semiconductor device under test for indications of the fault;

determining from the at least one electrical characteristic whether a fault condition exists; and

in response to determining the fault condition exists;

diverting power from a probe in electrical contact with the fault, and

turning off a power supply supplying power to the power line.

37. The method of claim 36, wherein the diverting comprises disconnecting the probe from the power supply.

38. The method of claim 36, wherein the diverting comprises connecting the probe to ground.

39. The method of claim 36, wherein:

the probe is one of a plurality of probes of a probe card assembly configured to contact a plurality of terminals of the semiconductor device, and

the monitoring comprises monitoring a portion of the power line disposed on the probe card assembly.

40. The method of claim 39, wherein the determining comprises comparing a voltage on the power line to a reference voltage.

41. The method of claim 39, wherein the fault is a short to ground.

42. The method of claim 36, wherein the diverting comprises diverting a discharge from a capacitor electrically connected to the power line from the probe.

43. The method of claim 36, wherein the monitoring comprises monitoring the at least one electrical characteristic at a plurality of locations on a power plane, wherein the power plane is electrically connected through the power line to a power supply, and a plurality of probes are electrically connected to the power plane and disposed to contact a plurality of terminals of a plurality of electronic devices.

44. The method of claim 43, wherein the monitoring further comprises determining whether a difference in voltages between at least one pair of locations on the plane exceeds a predetermined threshold.