System and method for communicating the synchronization status of memory modules during initialization of the memory modules

• US 20060218331A1
• Filed: 05/10/2006
• Published: 09/28/2006
• Est. Priority Date: 05/17/2004
• Status: Active Grant

• Current Assignee: Ralph James
• Original Assignee: Ralph James
• Inventors: James, Ralph
• Granted Patent: US 7,266,633 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during initialization. The memory hub controller and the memory hubs each transmit an initialization complete signal downstream when at least one receiver in the controller or hub is initialized and, in the case of the memory hubs, when a downstream initialization signal has also been received. Similarly, the memory hubs transmit an initialization signal upstream to another memory hub or the controller when both of its receivers are initialized and an upstream initialization signal has also been received. Receipt of an upstream initialization signal by the memory hub controller signifies that all of the receivers have been initialized.

Claims

1-73. -73. (canceled)

74. A method of initializing a memory system having a controller coupled to a plurality of memory hubs each of which includes a respective receiver, each receiver operable to utilize a respective receive clock signal, the method comprising:

receiving predetermined test data at each of the memory hubs;

capturing the predetermined test data at the receiver of each of the memory hubs, and wherein the act of capturing the predetermined test data in a first memory hub of the plurality of memory hubs comprises adjusting a phase of the respective receive clock signal utilized by the receiver in the first memory hub;

transmitting an initialization complete signal from each of the memory hubs responsive to the capture of the predetermined test data in the respective memory hub; and

receiving the initialization complete signal at the controller after each of the memory hubs has transmitted the initialization complete signal.

75. The method of claim 74 wherein the predetermined test data comprises a sequence of bits.

76. The method of claim 74 wherein the act of adjusting the phase of the receive clock signal is performed at each of the memory hubs.

77. The method of claim 74 wherein the initialization complete signal comprises a string of bits.

78. The method of claim 74 wherein the initialization complete signal comprises inverted predetermined test data.

79. The method of claim 74 further comprising:

transmitting the predetermined test data from the controller to an initial one of the memory hubs; and

transmitting the predetermined test data from the initial one of the memory hubs to a second one of the memory hubs responsive to the first one of the memory hubs capturing the predetermined test data.

80. The method of claim 74 wherein the act of adjusting the phase of the receive clock signal comprises comparing received data to the predetermined test data.

81. The method of claim 74 wherein the act of transmitting the initialization complete signal in a second one of the memory hubs is further responsive to receiving the initialization complete signal from a third one of the memory hubs.

82. The method of claim 81 wherein the second one of the memory hubs transmits the initialization complete signal to the controller.

83. The method of claim 74 further comprising transitioning the memory system to normal operation responsive to receiving the initialization complete signal at the controller.

84. The method of claim 74 wherein each of the respective receive clock signals comprises an internal signal generated by each respective memory hub.

85. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the plurality of memory devices, the memory hub comprising;

a receiver operable to receive predetermined test data, the receiver further operable to utilize an internal receive clock signal, the receiver comprising phase adjustment logic operable to adjust a phase of the receive clock signal to capture the predetermined test data; and

a transmitter operable to transmit an initialization complete signal responsive to the capture of the predetermined test data.

86. The memory module of claim 85 wherein the memory devices comprise dynamic random access memory devices.

87. The memory module of claim 85 wherein the transmitter is operable to transmit the initialization complete signal further responsive to receipt of the initialization complete signal by the receiver.

88. The memory module of claim 85 wherein the predetermined test data comprises a series of binary values and the initialization complete signal comprises the compliment of the binary values.

89. The memory module of claim 85 wherein the memory hub further comprises a second transmitter operable to transmit the predetermined test data responsive to the receipt of the predetermined test data by the receiver.

90. The memory module of claim 85 wherein the receiver further comprises a pattern comparator coupled to the phase adjustment logic, the pattern comparator operable to compare received data to the predetermined test data.

91. The memory module of claim 85 wherein the memory hub further comprises a second receiver operable to receive the initialization complete signal, the transmitter operable to transmit the initialization complete signal responsive to receipt of the initialization complete signal by the second receiver.

92. A memory system, comprising:

a memory hub controller operable to transmit predetermined test data and receive an initialization complete signal, the memory hub controller further operable to transition the memory system to normal operation responsive to the initialization complete signal; and

a memory module coupled to the memory hub controller, the memory module comprising;

a plurality of memory devices; and

a memory hub coupled to the plurality of memory devices, the memory hub comprising;

a receiver operable to receive the predetermined test data, the receiver further operable to utilize an internal receive clock signal, the receiver comprising phase adjustment logic operable to adjust a phase of the receive clock signal to capture the predetermined test data; and

a transmitter operable to transmit the initialization complete signal responsive to the capture of the predetermined test data.

93. The memory system of claim 92 wherein the memory devices comprise dynamic random access memory devices.

94. The memory system of claim 92 wherein the transmitter is operable to transmit the initialization complete signal further responsive to receipt of the initialization complete signal by the receiver.

95. The memory system of claim 92 wherein the predetermined test data comprises a series of binary values and the initialization complete signal comprises the compliment of the binary values.

96. The memory system of claim 92 wherein the memory hub further comprises a second transmitter operable to transmit the predetermined test data responsive to the receipt of the predetermined test data by the receiver.

97. The memory system of claim 92 wherein the receiver further comprises a pattern comparator coupled to the phase adjustment logic, the pattern comparator operable to compare received data to the predetermined test data.

98. The memory system of claim 92 wherein the memory hub further comprises a second receiver operable to receive the initialization complete signal, the transmitter operable to transmit the initialization complete signal responsive to receipt of the initialization complete signal by the second receiver.

99. The memory system of claim 92 further comprising a plurality of the memory modules coupled in a chain from the memory hub controller to a terminating memory module.

100. The memory system of claim 99 wherein the terminating memory module is operable to begin transmission of the initialization complete signal on capture of the predetermined test data.

101. The memory system of claim 100 wherein the terminating memory module is operable to couple the initialization complete signal to a next memory module in the chain.

102. The memory system of claim 101 wherein the first memory module is operable to transmit the initialization signal to the memory hub controller.