Memory card

• US 20060218347A1
• Filed: 08/17/2005
• Published: 09/28/2006
• Est. Priority Date: 03/25/2005
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Oshima, Takashi
• Application Number:
  US11/205,125
• Publication Number:
  US 20060218347A1
• Time in Patent Office: Days
• US Class Current: 711/115
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/7202 Allocation control and policies

Abstract

A memory card includes a first memory including first areas and second areas. A computing section gives an instruction to write writing data with an address assigned by a host unit into the first memory. A second memory stores an address unequal to an expected value. The address with the expected value is continuous with the address of the data last written. A first counter counts a number of requests to write the writing data of the address unequal to the expected value for each of the addresses. A third memory stores the address whose value in the first counter has reached a first set value. When receiving a request to write the writing data of the address stored in the third memory, the computing section gives an instruction to write the writing data into an unwritten part of the second areas, regardless of the address.

Claims

1. A memory card comprising:

a first memory including a plurality of first areas and a plurality of second areas, the first areas and the second areas being composed of a plurality of write unit areas;

a computing section giving an instruction to write writing data with an address assigned by a host unit into the first memory;

a second memory storing an address unequal to an expected value, the address with the expected value being continuous with the address of the data last written;

a first counter counting, for each of the addresses, a number of requests to write the writing data of the address unequal to the expected value; and

a third memory storing the address whose value in the first counter has reached a first set value,

wherein the computing section, when receiving a request to write the writing data of the address stored in the third memory, gives an instruction to write the writing data into an unwritten part of the second areas, regardless of the address.

2. The memory card according to claim 1, wherein the computing section gives an instruction to write the writing data of the address unequal to the expected value into an unwritten part of the first area.

3. The memory card according to claim 1, further comprising a second counter which sets a value for the address of the writing data to an initial value each time the writing data is written into the second area.

4. The memory card according to claim 3, wherein the computing section gives an instruction to copy a latest writing data of each of the addresses stored in one of the second areas into a new second area which is another one of the second areas, and

the second counter changes the value for the address of the writing data copied into the new second area.

5. The memory card according to claim 4, wherein the computing section copies the writing data of the address whose value in the second counter has reached a second set value into one of the first areas, and

after the writing data of the address whose value has reached the second set value is copied, the address of the writing data copied is deleted from the third memory.

6. The memory card according to claim 1, wherein the first areas and the second areas are data erase units of the first memory.

7. The memory card according to claim 6, wherein the first memory is a NAND flash memory.

8. The memory card according to claim 1, wherein a specific number of consecutive addresses form a group, and

the computing section, when the data of the addresses belonging to a same group are written in two of the first areas, gives an instruction to write the data written in an old first area, which is one of the two of the first areas, into a new first area, which is another one of the two of the first areas, and gives an instruction to erase the data in the old first area.

9. The memory card according to claim 8, wherein the computing section gives an instruction to additionally write the writing data of the address stored in the third memory into an unwritten part of the second areas.

10. A memory card comprising:

a memory including a plurality of first areas and a plurality of second areas, the first areas and the second areas being composed of a plurality of write unit areas; and

a computing section giving an instruction to write writing data with an address assigned by a host unit into the memory,

wherein the computing section, when receiving a request to write the writing data of an address unequal to an expected value which is continuous with the address of the data last written, gives an instruction to write the writing data into an unwritten part of the second areas, regardless of the address.

11. The memory card according to claim 10, wherein the computing section gives an instruction to write the writing data of the address unequal to the expected value into an unwritten part of the first area.

12. The memory card according to claim 10, wherein the computing section gives an instruction to copy a latest writing data of each of the addresses stored in one of the second areas into a new second area which is another one of the second areas.

13. The memory card according to claim 10, wherein the first areas and the second areas are data erase units of the memory.

14. The memory card according to claim 13, wherein the memory is a NAND flash memory.

15. The memory card according to claim 10, wherein a specific number of consecutive addresses form a group, and

the computing section, when the data of the addresses belonging to a same group are written in two of the first areas, gives an instruction to write the data written in an old first area, which is one of the two of the first areas, into a new first area, which is another one of the two of the first areas, and gives an instruction to erase the data in the old first area.