Method and system for managing multi-plane memory devices

• US 20060218359A1
• Filed: 03/22/2005
• Published: 09/28/2006
• Est. Priority Date: 03/22/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Sanders, Richard, Zeevi, Josef
• Granted Patent: US 7,627,712 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory device and represents a second block from a second plane of the multi-plane solid state memory device.

Claims

1. A computational system comprising:

a controller; and

a multi-plane solid state memory device accessible to the controller;

wherein the controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory device and that represents a second block from a second plane of the multi-plane solid state memory device.

2. The computational system of claim 1, wherein the controller is configured to write a first virtually addressed page to a first page of the first plane and to write a second virtually addressed page to a first page of the second plane, the second virtually addressed page located sequentially next to the first virtually addressed page.

3. The computational system of claim 2, wherein the first page of the first plane and the second page of the second plane have the same within plane address.

4. The computational system of claim 2, wherein writing to the first virtually addressed page and writing to the second virtually addressed page is performed substantially simultaneously.

5. The computational system of claim 1, wherein the controller is configured to read a first virtually addressed page from a first page of the first plane and read a second virtually addressed page from a second page of the second plane.

6. The computational system of claim 5, wherein the first page and the second page are physical pages having the same within plane address.

7. The computational system of claim 5, wherein the first page of the first plane and the second page of the second plane are read concurrently.

8. The computational system of claim 1, wherein the virtual block has a size of a sum of a size of the first block and a size of the second block.

9. The computational system of claim 1, wherein the virtual block includes a number of virtual pages at least equal to a sum of a number of pages in the first block and a number of pages in the second block.

10. The computational system of claim 1, wherein the virtual block further represents a third block of a third plane.

11. The computational system of claim 1, wherein the controller is configured to erase the virtual block by directing the multi-plane solid state memory device to erase the first block and the second block.

12. The computational system of claim 11, wherein multi-plane solid state memory device is configured to erase the first block and the second block substantially simultaneously.

13. A method of controlling a multi-plane solid state memory device, the method comprising:

accessing a first virtual page representing a first page of a first plane located at a particular block address; and

accessing a second virtual page sequentially next to the first virtual page, the second virtual page representing a second page of a second plane located at the particular block address.

14. The method of claim 13, wherein accessing the first virtual page and accessing the second virtual page are performed substantially simultaneously.

15. The method of claim 13, wherein accessing the first virtual page includes writing to the first page.

16. The method of claim 13, wherein accessing the first virtual page includes reading the first page.

17. The method of claim 13, further comprising accessing a third virtual page addressed sequentially next to the second virtual page, the third virtual page representing a third page addressed at a sequentially located block address with respect to the particular block address.

18. A method of controlling a multi-plane solid state memory device, the method comprising:

receiving a command to erase a virtual block, the virtual block representing a first block of a first plane and a second block of a second plane;

erasing the first block of the first plane; and

erasing the second block of the second plane.

19. The method of claim 18, wherein erasing the first block and erasing the second block are performed concurrently.

20. The method of claim 18, wherein the first block is located at a particular block address within the first plane and wherein the second block is located at the particular block address within the second plane.

21. The method of claim 18, wherein the first block is located at a first block address within the first plane and wherein the second block is located at a second block address within the second plane, wherein the second block address is different from the first block address.

22. The method of claim 18, wherein the virtual block further represents a third block of a third plane, the method further comprising erasing the third block of the third plane.