Integrated circuit margin stress test system

• US 20060218455A1
• Filed: 03/23/2005
• Published: 09/28/2006
• Est. Priority Date: 03/23/2005
• Status: Abandoned Application

• Current Assignee: Silicon Design Solution Incorporated
• Original Assignee: Silicon Design Solution Incorporated
• Inventors: Nguyen, Hieu Dinh, Bligh, Kevin Owen, LeClair, Kevin Robert, Le, Chuong Tien, Tran, Duytan Kiem, Wik, Thomas Robert
• Application Number:
  US11/089,300
• Publication Number:
  US 20060218455A1
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

Systems and methods are disclosed for testing a synchronous memory system by electrically stressing one or more electrical conditions of the component circuits; providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and providing a test stimuli during testing. In another aspect, the memory system testing includes setting a self-timed control input of the memory system to a predetermined self timed period value; and testing the memory based on the predetermined self timed period value.

Claims

1. A system for testing an integrated circuit device having component circuits therein, comprising:

a stress circuit to vary one or more electrical conditions of the component circuits;

an on-chip test controller coupled to the stress circuit to control an electrical stress during device testing; and

an external tester coupled to the on-chip test controller to provide the electrical stress and to provide test stimuli during testing, the external tester leaving the integrated circuit device in an unstressed mode during field operation.

2. The system of claim 1, wherein the on-chip test controller consists of a Built-In Self-Test (BIST) controller or a scan chain.

3. The system of claim 1, wherein the electrical stress reduces the timing margin or the sensing margin of the component circuits.

4. The system of claim 1, wherein the component circuits comprise one or more memory instances.

5. The system of claim 4, wherein the memory instances are subjected to stressed electrical conditions that reduce at least one of:

a memory cell'"'"'s read margin, a memory cell'"'"'s write margin, or a sense amplifier'"'"'s sensing margin.

6. The system of claim 4, wherein the memory arrays comprise embedded memories contained in an SOC (System-On-a-Chip) integrated circuit.

7. The system of claim 4, comprising a sense amplifier, wherein the embedded memory arrays are electrically stressed by reducing time allowed for read signal development before the sense amplifier is latched to make the cells in the memory arrays more susceptible to failure during the margin test mode.

8. The system of claim 4, wherein time allocated for a read signal development is reduced by changing a Self-Time Period (STP) of the sense amplifier and word line timing circuits of a memory instance generated from a memory compiler.

9. A memory system, comprising:

a synchronous memory array having self-timed period (STP) control input; and

a test controller coupled to the self-timed control input of the synchronous memory array to vary the memory'"'"'s self-time period during testing.

10. The memory system of claim 9, wherein the test controller comprises:

means for setting the self-timed control input to a predetermined self timed period value; and

means for testing the synchronous memory based on the predetermined self timed period value.

11. The memory system of claim 9, comprising means for varying the self timed period value.

12. The memory system of claim 9, comprising

means for:

setting the self-timed control input to a nominal self timed period value; and

means for testing the synchronous memory.

13. The memory system of claim 12, comprising means for

means for increasing the self-timed control input from the nominal self timed period value;

and

means for testing the synchronous memory.

14. The memory system of claim 13, comprising means for:

means for decreasing the self-timed control input from the nominal self-timed period value; and

means for testing the synchronous memory.

15. The memory system of claim 9, comprising an STP control circuit coupled to the STP control signals.

16. The memory system of claim 15, comprising reference columns coupled to the STP control circuit.

17. The memory system of claim 9, comprising a row decoder coupled to the STP control circuit.

18. The memory system of claim 9, comprising reference columns coupled to the STP control circuit.

19. The memory system of claim 9, wherein the test controller comprises one of:

an external ATE tester, a built-in-self-test (BIST) controller.

20. A method for testing a synchronous memory system having a self-timed control input, comprising:

a. setting the self-timed control input to a predetermined self timed period value; and

b. testing the synchronous memory based on the predetermined self timed period value.

21. The method of claim 20, comprising varying the self timed period value.

22. The method of claim 20, comprising

setting the self-timed control input to a nominal self timed period value;

and

testing the synchronous memory.

23. The method of claim 20, comprising:

setting the self-timed control input to an increased self timed period value; and

testing the synchronous memory.

24. The method of claim 20, comprising:

setting the self-timed control input to a decreased self timed period value; and

testing the synchronous memory.

25. The method of claim 20, comprising disabling the self-timed control input during operation.

26. The method of claim 20, comprising enabling the self-timed control input during operation.

27. The method of claim 20, comprising testing using one of:

an external ATE, and a built-in-self-test (BIST) controller.

28. A method for testing embedded synchronous memory in an integrated circuit, the method comprising:

generating an expected data value;

setting a self timed period value for the synchronous memory;

delivering test data, separate from control data and address data, to the memory;

reading an actual data value from the memory corresponding to the delivered test data; and

comparing the actual data value to the expected data value.

29. A method for testing an integrated circuit device having component circuits therein, comprising:

electrically stressing one or more electrical conditions of the component circuits;

providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and

providing a test stimuli during testing.

30. The method of claim 29, wherein the component circuits comprise one or more memory arrays.

31. The method of claim 30, comprising subjecting the memory array to stressed electrical conditions that reduce at least one of:

a memory cell read/write margin and a sense amplifier margin.