HERMETIC CAP LAYERS FORMED ON LOW-K FILMS BY PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION

• US 20060219174A1
• Filed: 06/12/2006
• Published: 10/05/2006
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Kim, Bok Hoen, Yim, Kang Sub, Nguyen, Vu Ngoc Tran
• Granted Patent: US 7,399,364 B2
• Time in Patent Office: Days
• US Class Current: 118/723.R
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02315 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

A method of forming a cap layer over a dielectric layer on a substrate including forming a plasma from a process gas including oxygen and tetraethoxysilane, and depositing the cap layer on the dielectric layer, where the cap layer comprises a thickness of about 600 Å or less, and a compressive stress of about 200 MPa or more. Also, a method of forming a cap layer over a dielectric layer on a substrate including forming a process gas by flowing together about 200 mgm to about 8000 mgm of tetraethoxysilane, about 2000 to about 20000 sccm of oxygen (O₂), and about 2000 sccm to about 20000 sccm of carrier gas, generating a plasma from the process gas, where one or more RF generators supply about 50 watts to about 100 watts of low frequency RF power to the plasma, and about 100 watts to about 600 watts of high frequency RF power to the plasma, and depositing the cap layer on the dielectric layer.

Claims

1-23. -23. (canceled)

24. A system for forming a cap layer over a dielectric layer on a substrate, the system comprising:

a housing configured to form a processing chamber;

a gas distribution system to flow about 200 mgm to about 8000 mgm of a silicon containing precursor, about 2000 to about 20000 sccm of oxygen (O₂), and about 2000 sccm to about 20000 sccm of carrier gas through a gas distribution faceplate and into the processing chamber;

a plasma generation system configured to form a plasma within said processing chamber, wherein said plasma generation system comprises one or more RF generators that supply about 50 watts to about 100 watts of low frequency RF power to the plasma, and about 100 watts to about 600 watts of high frequency RF power to the plasma; and

a substrate holder configured to hold the substrate about 350 to about 450 mils from the gas distribution faceplate within the processing chamber, wherein the cap layer formed has a thickness of about 600 Å

or less.

25. The system of claim 24, wherein the cap layer has a compressive stress of about 200 MPa or more.

26. The system of claim 24, wherein the dielectric layer is a low-κ

dielectric layer comprising silicon and carbon.

27. The system of claim 24, wherein the cap layer comprises undoped silicate glass.

28. The system of claim 24, wherein the silicon containing precursor comprises silane, tetraethoxysilane, or octamethylcyclotetrasiloxane.

29. The system of claim 24, wherein the thickness of the cap layer is about 200 Å

to about 600 Å

.

30. The system of claim 24, wherein the cap layer has a compressive stress of about 200 MPa to about 300 MPa.

31. The system of claim 24, the substrate comprises a 200 mm or 300 mm silicon wafer.

32. An integrated circuit device comprising:

a silicon substrate;

a low-κ

dielectric layer deposited on the substrate, wherein the low-κ

layer has a κ

-value of about 4 or less; and

a cap layer formed on the low-κ

layer, wherein the cap layer has a thickness of about 600 Å

or less and a compressive stress level of about 200 MPa or more.

33. The integrated circuit device of claim 32, wherein the silicon substrate comprises a 200 mm or 300 mm silicon wafer.

34. The integrated circuit device of claim 32, wherein the low-κ

layer comprises silicon oxycarbide, parylene, amorphous fluorinated carbon, or hydrogen silsesquioxane.

35. The integrated circuit device of claim 32, wherein the cap layer has a thickness of about 200 Å

to about 600 Å

.

36. The integrated circuit device of claim 32, wherein the compressive stress level of the cap layer is about 200 MPa to about 300 MPa.

37. The integrated circuit device of claim 32, wherein the cap layer comprises silicon dioxide.

38. The integrated circuit device of claim 32, wherein the device further comprises an anti-reflective coating formed on the cap layer.

39. An integrated circuit device comprising:

a silicon substrate;

a barrier layer formed on the silicon substrate;

a first dielectric layer formed on the barrier layer;

an etch stop layer formed on the first dielectric layer;

a second dielectric layer formed on the etch stop layer;

a cap layer formed on the second dielectric layer, wherein the cap layer has a thickness of about 600 Å

or less and a compressive stress level of about 200 MPa or more; and

a trench extending from the barrier layer through the cap layer, wherein the trench is filled with a conductive material to form an interconnect.

40. The integrated circuit device of claim 39, wherein the barrier layer comprises silicon nitride.

41. The integrated circuit device of claim 39, wherein the cap layer comprises plasma deposited silicon oxide.

42. The integrated circuit device of claim 39, wherein the cap layer has a thickness of about 200 Å

to about 600 Å

.

43. The integrated circuit device of claim 39, wherein the compressive stress level of the cap layer is about 200 MPa to about 300 MPa.

44. The integrated circuit device of claim 39, wherein the conductive material in the trench comprises aluminum or copper.

45. The integrated circuit device of claim 39, wherein the conductive material in the trench comprises an alloy of silicon with a second metal comprising titanium, nickel or cobalt.

46. The integrated circuit device of claim 39, wherein the device further comprises an anti-reflective coating formed on the cap layer.