Logic gate with a potential-free gate electrode for organic integrated circuits

• US 20060220005A1
• Filed: 06/30/2004
• Published: 10/05/2006
• Est. Priority Date: 07/03/2003
• Status: Abandoned Application

• Current Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Inventors: Glauert, Wolfram, Fix, Walter, Ullmann, Andreas
• Application Number:
  US10/562,869
• Publication Number:
  US 20060220005A1
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H10K 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
• CPC Class Codes: H10K 19/80 Interconnections, e.g. terminals

Abstract

The invention relates to an organic logic gate comprising at least one charging field effect transistor (charging FET) and at least one switching field effect transistor (switching FET), the charging FET having at least one gate electrode, a source electrode and a drain electrode, the gate electrode of the charging FET being potential-free.

Claims

1. An organic logic gate comprising:

a circuit having an output and comprising at least one charging field effect transistor (charging FET) having source, drain and gate electrodes and at least one switching field effect transistor (switching FET) having at least one gate electrode, a source electrode and a drain electrode, the drain-source electrodes of the charging and switching transistors being arranged to be coupled in series between a voltage source and a reference potential such that the gate electrode of the charging FET is not connected via an electrical line directly to the voltage source, to the reference potential or to the output.

2. The organic logic gate as claimed in claim 1 wherein the gate electrode of the charging FET is capacitively coupled to the source electrode of the charging FET.

3. The organic logic gate as claimed in claim 2 wherein the capacitive coupling is achieved by the gate electrode of the charging FET overlapping the source electrode of the charging FET.

4. The organic logic gate as claimed in claim 1 wherein the gate electrode of the charging FET is resistively coupled to the source electrode of the charging FET.

5. The organic logic gate as claimed in claim 1 wherein the gate electrode of the charging FET is capacitively coupled to the drain electrode of the charging FET.

6. The organic logic gate as claimed in claim 5 wherein the capacitive coupling is achieved by the drain electrode overlapping the gate electrode of the charging FET.

7. The organic logic gate as claimed in claim 1 wherein the gate electrode of the charging FET is resistively coupled to the drain electrode of the charging FET.

8. The organic logic gate as claimed in claim 1 wherein the organic logic gate is constructed without plated-through holes.