Semiconductor device and manufacturing method thereof

• US 20060220142A1
• Filed: 06/29/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Naoyoshi
• Granted Patent: US 7,821,077 B2
• Time in Patent Office: Days
• US Class Current: 257/374
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.

Claims

1. A semiconductor device comprising:

an element isolation structure in which trenches formed in an element isolation region on a semiconductor substrate are filled up with insulating materials;

a first conductivity type element formed in a first active region divided by said element isolation structure; and

a second conductivity type element formed in a second active region divided by said element isolation structure,

said element isolation structure comprising;

a first element isolation region of said element isolation region including regions adjacent to a pair of opposed ends of said second active region, said first element isolation region being filled with an insulating material that gives a compressive stress to said second active region; and

a second element isolation region of said element isolation region other than said first element isolation region, said second element isolation region being filled with an insulating material that gives a tensile stress to each of said first and second active regions.

2. The semiconductor device according to claim 1, wherein a gate electrode is formed into a pattern on each of said first and second active regions with a gate insulating film being interposed, and the gate electrode on said second active region extends parallel to said first element isolation region.

3. The semiconductor device according to claim 1, wherein either of said first and second conductivity type elements is a transistor, and said pair of opposed ends of said second active region are both ends of said second active region parallel to a width of a gate of the second conductivity type transistor.

4. The semiconductor device according to claim 1, wherein first and second conductivity type elements are alternately arranged, and said first element isolation region is formed between each pair of first and second conductivity type elements.

5. The semiconductor device according to claim 1, wherein a first conductivity type element group is constituted by a plurality of first conductivity type elements arranged, each second conductivity type element, and each second conductivity type element and said first conductivity type element group are formed in areas on said semiconductor substrate independent of each other, and said first element isolation region is formed so as to sandwich therein each second active region.

6. The semiconductor device according to claim 5, wherein dummy active regions are formed at both ends of each second conductivity type element.

7. The semiconductor device according to claim 1, wherein a first conductivity type element group constituted by a plurality of first conductivity type elements arranged and a second conductivity type element group constituted by a plurality of second conductivity type elements arranged are formed in areas on said semiconductor substrate independent of each other, and said first element isolation region is formed so as to sandwich therein each second active region of said second conductivity type element group.

8. The semiconductor device according to claim 7, wherein dummy active regions are formed at both ends of said second conductivity type element group.

9. The semiconductor device according to claim 1, wherein only an upper layer portion of said first element isolation region is filled with said insulating material that gives a compressive stress.

10. The semiconductor device according to claim 9, wherein a lower layer portion of said first element isolation region is filled with the same insulating material as said insulating material in said second element isolation region that gives a tensile stress.

11. The semiconductor device according to claim 1, wherein upper and lower layer portions of said first element isolation region are filled with different insulating materials that give compressive stresses.

12. The semiconductor device according to claim 1, wherein said insulating material that gives a compressive stress is one selected from a group of highly dense plasma oxide, oxide of amorphous silicon, and oxide of polycrystalline silicon, and said insulating material that gives a tensile stress is silicon oxide deposited at a temperature not more than its glass transition temperature.

13. A manufacturing method of a semiconductor device in which first and second active regions are divided by an element isolation structure formed in an element isolation region on a semiconductor substrate, and first and second conductivity type elements are formed in said first and second active regions, respectively,

said element isolation region comprising a first element isolation region including regions adjacent to a pair of opposed ends of said second active region, and a second element isolation region other than said first element isolation region,

said method comprising the steps of:

forming a first trench in said second element isolation region on said semiconductor substrate, and filling up said first trench with an insulating material that gives a tensile stress to each of said first and second active regions; and

forming a second trench in said first element isolation region on said semiconductor substrate, and filling up said second trench with an insulating material that gives a compressive stress to said second active region.

14. The method according to claim 13, further comprising a step of forming a gate electrode into a pattern on each of said first and second active regions with a gate insulating film being interposed, so that the gate electrode on said second active region extends parallel to said first element isolation region.

15. The method according to claim 13, wherein upper and lower layer portions of said first element isolation region are filled with different insulating materials that give compressive stresses.

16. The method according to claim 13, wherein said insulating material that gives a compressive stress is one selected from a group of highly dense plasma oxide, oxide of amorphous silicon, and oxide of polycrystalline silicon, and said insulating material that gives a tensile stress is silicon oxide deposited at a temperature not more than its glass transition temperature.

17. A manufacturing method of a semiconductor device in which first and second active regions are divided by an element isolation structure formed in an element isolation region on a semiconductor substrate, and first and second conductivity type elements are formed in said first and second active regions, respectively,

said element isolation region comprising a first element isolation region including regions adjacent to a pair of opposed ends of said second active region, and a second element isolation region other than said first element isolation region,

said method comprising the steps of:

forming a first trench in said element isolation region on said semiconductor substrate, and filling up said first trench with an insulating material that gives a tensile stress to each of said first and second active regions; and

forming a second trench in a portion of said insulating material having filled up said first trench to give a tensile stress, corresponding to said first element isolation region, and filling up said second trench with an insulating material that gives a compressive stress to said second active region.

18. The method according to claim 17, further comprising a step of forming a gate electrode into a pattern on each of said first and second active regions with a gate insulating film being interposed, so that the gate electrode on said second active region extends parallel to said first element isolation region.

19. The method according to claim 17, wherein said insulating material that gives a compressive stress is one selected from a group of highly dense plasma oxide, oxide of amorphous silicon, and oxide of polycrystalline silicon, and said insulating material that gives a tensile stress is silicon oxide deposited at a temperature not more than its glass transition temperature.