Terminal layer setting method for semiconductor circuit having a plurality of circuit layers, storage media storing terminal layer setting program, storage media storing a wiring terminal extension processing program and terminal extending component used for setting of the terminal layer

• US 20060220255A1
• Filed: 09/28/2005
• Published: 10/05/2006
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Oba, Hisayoshi
• Granted Patent: US 7,725,865 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A terminal layer setting method according to the present invention is a method for a computer setting up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprises the steps of obtaining various kinds of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; comparing between a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with a cell or macro at a connecting destination; and setting up a terminal layer which is a wiring layer at an extending destination of a wiring terminal for the subject cell or macro based on the comparison result.

Claims

1. A terminal layer setting method, in the method for a computer setting up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprising:

obtaining various kinds of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer;

comparing between a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with a cell or macro at a connecting destination; and

setting up a terminal layer which is a wiring layer at an extending destination of a wiring terminal of the subject cell or macro based on the comparison result.

2. The terminal layer setting method according to claim 1, wherein extending a wiring terminal of said cell or macro to a wiring layer set up as an extending destination in a shortest path.

3. The terminal layer setting method according to claim 2, wherein extending a wiring terminal of a subject cell or macro to a wiring layer, which is set up as an extending destination, by adding a necessary number of terminal extending components, each of which comprises a Via and a wiring having a length thereof for adequately securing a contact with the Via, in the normal direction to a surface which the subject cell or macro is mounted onto.

4. The terminal layer setting method according to claim 1, wherein, if a wiring routing is required between said subject cell or macro and a cell or macro at a connecting destination of the subject cell or macro, a terminal layer is set up on a wiring layer which is set as said extending destination and on the neighboring wiring layer so as to make it possible to route wiring on the neighboring layer of a wiring layer that is specified as the extending destination.

5. The terminal layer setting method according to claim 1, wherein, if a driving capability of obtained subject cell or macro is larger than a wiring resistance based on a distance between the subject cell or macro and a cell or macro at a connecting destination in said comparison, a wiring layer is set up for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a large wiring resistance per unit length of wiring.

6. The terminal layer setting method according to claim 1, wherein, if a driving capability of obtained subject cell or macro is smaller than a wiring resistance based on a distance between the subject cell or macro and a cell or macro at a connecting destination in said comparison, a wiring layer is set up for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a small wiring resistance per unit length of wiring.

7. The terminal layer setting method according to claim 1, further comprising the steps of

judging whether or not a subject cell or macro is connected with a certain number, or greater, of cells or macros at connecting destinations;

and

setting up a wiring layer of a wiring terminal of the subject cell or macro at an extending destination between wiring layers having a small wiring capacitance per unit length of wiring, if the subject cell or macro is judged to be connected to more than or equal to the certain number of cells or macros at the connecting destination.

8. The terminal layer setting method according to claim 1, further comprising the steps of

identifying an area on said board where wiring between said cells or macros and cells or macros at a connecting destination is congested based on obtained information;

and

setting up wiring layers for the cell or macro at an extending destination among a plurality of wiring layers in a distributed manner for the cells or macros included in an area where it is judged to be congested by wiring.

9. A terminal layer setting method, in a method for a computer setting up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprising:

obtaining various kinds of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer;

setting up terminal layers, which are wiring layers at an extending destination of the plurality of cells or macros, by using a certain logic based on the obtained information so as to allocate, in a well-balanced manner, the plurality of wiring layers; and

extending wiring terminals of the plurality of cells or macros to wiring layers set up as extending destinations in the shortest paths.

10. A storage media storing a terminal layer setting program, in the program for making a computer set up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprising:

obtaining a various kind of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer;

comparing between a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with a cell or macro at a connecting destination; and

setting up a terminal layer which is a wiring layer at an extending destination of a wiring terminal of the subject cell or macro based on the comparison result.

11. The storage media storing the terminal layer setting program according to claim 10, wherein said program further comprising the step of designating to extend a wiring terminal of said plurality of cells or macros to a wiring layer set as an extending destination in the shortest path.

14. The storage media storing the terminal layer setting program according to claim 10, wherein said program further comprising the step of setting up a terminal layer on a wiring layer, which is set as said extending destination, and on the neighboring wiring layer so as to make it possible to route wiring on the neighboring layer of a wiring layer that is specified as the extending destination if a wiring routing is required between said subject cell or macro and a cell or macro at a connecting destination of the subject cell or macro.

15. The storage media storing the terminal layer setting program according to claim 10, wherein, if a driving capability of obtained subject cell or macro is larger than a wiring resistance based on a distance between the subject cell or macro and a cell or macro at a connecting destination in said comparison step, a wiring layer is set up for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a large wiring resistance per unit length of wiring.

16. The storage media storing the terminal layer setting program according to claim 10, wherein, if a driving capability of obtained subject cell or macro is smaller than a wiring resistance based on a distance between the subject cell or macro and a cell or macro at a connecting destination in said comparison, a wiring layer is setup for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a small wiring resistance per unit length of wiring.

17. The storage media storing the terminal layer setting program according to claim 10, further comprising the steps of judging whether or not a subject cell or macro is connected with a certain number, or greater, of cells or macros at connecting destinations;

and setting up a wiring layer of a wiring terminal of the subject cell or macro at an extending destination between wiring layers having a small wiring capacitance per unit length of wiring, if the subject cell or macro is judged to be connected to more than or equal to the certain number of cells or macros at connecting destination.

18. The storage media storing the terminal layer setting program according to claim 10, comprising the steps of identifying an area on said board where wiring between said cells or macros and cells or macros at a connecting destination are congested based on obtained information;

and setting up wiring layers for the cell or macro at an extending destination among a plurality of wiring layers in a distributed manner for the cells or macros included in the area where it is judged to be congested by wiring.

12. A storage media storing a wiring terminal extension processing program, in the program for making a computer execute an extension processing for a wiring terminal based on a result of setting up a terminal layer which is a layer at an extending destination of a wiring terminal of a cell or macro constituting a semiconductor circuit having a plurality of wiring layers, wherein

the program makes the computer execute:

extending a wiring terminal of a subject cell or macro to a wiring layer, which is set up as an extending destination, by adding a necessary number of terminal extending components, each of which comprises a Via and a wiring having a length thereof for adequately securing a contact with the Via, in the normal direction to a surface which the subject cell or macro is mounted onto.

13. The storage media storing the wiring terminal extension processing program according to claim 12, wherein a Via diameter of said Via and said length for adequately securing a contact are determined in accordance with a wiring size of wiring layer.

19. A storage media storing a terminal layer setting program, in the program for making a computer set up a terminal layer of a semiconductor circuit having a plurality of wiring layers, wherein the program makes the computer execute:

obtaining various kinds of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; and

setting up terminal layers, which are wiring layers at an extending destination of the plurality of cells or macros, by using a certain logic based on the obtained information so as to allocate, in a well-balanced manner, the plurality of wiring layers, and extending wiring terminals of the plurality of cells or macros to wiring layers set up as extending destinations in the shortest paths.

20. A terminal extending component, in the component used for setting up a terminal layer which is a wiring layer at an extending destination of a wiring terminal of a cell or macro constituting a semiconductor circuit having a plurality of wiring layers, wherein:

Said component is used for extending a wiring terminal of a subject cell or macro in a direction normal to a surface which the cell or macro is mounted onto, and comprising a Via and a wire having length for adequately securing a contact with the Via.

21. The terminal extending component according to claim 20, wherein a Via diameter of said Via and said length for adequately securing a contact are determined in accordance with a wiring size of wiring layer.