System and method for automatic power-up and power-down of an output video circuit

• US 20060220632A1
• Filed: 03/15/2005
• Published: 10/05/2006
• Est. Priority Date: 03/15/2005
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Koo, Ronald Bonshaw
• Granted Patent: US 8,125,572 B2
• Time in Patent Office: Days
• US Class Current: 323/299
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/147 using display panels
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time

Abstract

A system and method for configuring a video circuit into a low power consumption mode and a high power consumption mode. The system comprises an input signal detection circuit adapted to generate a first signal indicative of whether an input video signal is present at the input of the video circuit; an output load detection circuit adapted to generate a second signal indicative of whether a load is connected to the output of the video circuit; and a control device adapted to generate a third signal to control the power consumption mode of the video circuit in response to the first and second signals. The method entails detecting whether an input video signal is present; detecting whether the load is present; and configuring the video circuit for high power consumption if both the input video signal and the load are present, otherwise configuring the video circuit for low power consumption.

Claims

1. A system for configuring a video circuit into a relatively low power consumption mode or a relatively high power consumption mode, comprising:

an input signal detection circuit adapted to generate a first signal indicative of whether an input video signal is present at an input of said video circuit;

an output load detection circuit adapted to generate a second signal indicative of whether a load is connected to an output of said video circuit; and

a control device adapted to generate a third signal responsive to said first and second signals, wherein said third signal controls whether said video circuit is in said relatively low power consumption mode or in said relatively high power consumption mode.

2. The system of claim 1, wherein said input signal detection circuit comprises:

a first sub-circuit adapted to generate only a plurality of sync pulses from said input video signal;

a second sub-circuit adapted to generate edge-pulses for each edge of said sync pulses; and

a third sub-circuit adapted to generate said first signal comprising a first logic level in response to receiving a plurality of said edge-pulses, and a second logic level in response to not receiving said edge-pulses.

3. The system of claim 2, wherein said first sub-circuit comprises a comparator including a first input adapted to receive said input video signal, a second input adapted to receive a reference voltage, and an output coupled to said second sub-circuit.

4. The system of claim 2, wherein said second sub-circuit comprises:

a delay device adapted to receive said sync pulses generated by said first sub-circuit; and

an exclusive-OR gate including a first input adapted to receive said sync pulses generated by said first sub-circuit, and a second input coupled to an output of said delay device.

5. The system of claim 2, wherein said third sub-circuit comprises:

a first transistor including a first control input coupled to an output of said second sub-circuit, a first current input coupled to a power supply rail, and a first current output;

a second transistor including a second control input coupled to said output of said second sub-circuit, a second current output coupled to a ground potential rail, and a second current input coupled to said first current output of said first transistor;

a capacitor coupled between said first current output and said ground potential rail; and

an inverter coupled to said capacitor.

6. The system of claim 5, wherein said first transistor comprises a first field effect transistor, and/or said second transistor comprises a second field effect transistor.

7. The system of claim 5, wherein said first transistor comprises a first bipolar transistor, and/or said second transistor comprises a second bipolar transistor.

8. The system of claim 1, wherein said output load detection circuit comprises:

a first sub-circuit adapted to generate said second signal when said video circuit is in said relatively low power consumption mode; and

a second sub-circuit adapted to generate said second signal when said video circuit is in said relatively high power consumption mode.

9. The system of claim 8, wherein said first sub-circuit comprises:

a first sub-sub-circuit adapted to periodically generate a test current towards said output of said video circuit;

a second sub-sub-circuit adapted to compare a voltage at said output of said video circuit produced by said test current, with a reference voltage, and generate a logic level signal indicative of whether said voltage is above or below said reference voltage; and

a third sub-sub-circuit to produce said second signal comprising said logic level signal.

10. The system of claim 9,

wherein said first sub-sub circuit comprises:

an inverter including an input to receive a control signal including a plurality of test pulses;

a field effect transistor including a gate coupled to an output of said inverter, a source coupled to a power supply rail, and a drain; and

a resistive element coupled between said drain of said field effect transistor and said output of said video circuit;

wherein said second sub-sub-circuit comprises a latching comparator including a first input coupled to said output of said video circuit, a second input coupled to a reference voltage source, an output, and a latch enable input adapted to receive said control signal; and

wherein said third sub-sub-circuit comprises a NAND gate including a first input coupled to said output of said inverter, and a second input coupled to said output of said latching comparator.

11. The system of claim 8, wherein said second sub-circuit comprises:

a first sub-sub-circuit adapted to generate a test current proportional to a current at said output of said video circuit; and

a second sub-sub-circuit adapted to generate said second signal in response to said test current.

12. The system of claim 11,

wherein said first sub-sub-circuit comprises:

a first field effect transistor including a first gate coupled to a first output gate of a first output field effect transistor of said video circuit, a first source coupled to a power supply rail, and a first drain; and

a second field effect transistor including a second gate coupled to a second output gate of a second output field effect transistor of said video circuit, a second source coupled to a ground potential rail, and a second drain coupled to said first drain of said first field effect transistor;

wherein said second sub-sub-circuit comprises;

a resistive element coupled between said first and second drains, and said ground potential rail;

a peak detector including an input coupled to said first and second drains, and said ground potential rail; and

a comparator including a first input coupled to an output of said peak detector, a second input coupled to a reference voltage source, and an output adapted to generate said second signal.

13. The system of claim 1, wherein said control device comprises a state machine.

14. The system of claim 1, further comprising said video circuit.

15. The system of claim 14, wherein said video circuit comprises:

a low pass filter including an input adapted to receive said input video signal; and

a video amplifier including an input coupled to an output of said low pass filter.

16. A method for configuring a video circuit into a relatively low power consumption mode and a relatively high power consumption mode, comprising:

detecting whether an input video signal is present at an input of said video circuit;

detecting whether a load is connected to an output of said video circuit; and

configuring said video circuit into said relatively high power consumption mode if said input video signal is present at said input of said video circuit and said load is connected to said output of said video circuit, or configuring said video circuit into said relatively low power consumption mode if either or both said input video signal is not present at said input of said video circuit or said output load is not connected to said output of said video circuit.

17. The method of claim 16, wherein detecting whether said input video signal is present at said input of said video circuit comprises generating a logic level signal indicative of whether said input video signal is present at said input of said video circuit.

18. The method of claim 17, wherein generating said logic level signal comprises:

attempting to detect sync pulses of said input video signal; and

setting said logic level signal to a first state if said sync pulses of said input video signal are detected, or setting said logic level signal to a second state if said sync pulses of said input video signal are not detected.

19. The method of claim 18, wherein said sync pulses comprise composite sync pulses of said input video signal.

20. The method of claim 19, wherein generating said logic level signal comprises:

generating a first signal consisting of said composite sync pulses from said input video signal;

generating a second signal comprising edge-pulses resulting from respective edges of said composite sync pulses; and

processing said second signal to generate a third signal; and

generating said logic level signal from said third signal.

21. The method of claim 16, wherein detecting whether said load is connected to said output of said video circuit comprises generating a logic level signal indicative of whether said load is connected to said output of said video circuit.

22. The method of claim 21, wherein generating said logic level signal comprises:

forming a test current at said output of said video circuit;

setting said logic level signal to a first state if said test current is above a threshold level, or setting said logic level signal to a second state if said test current is below said threshold level.

23. The method of claim 21, wherein generating said logic level signal comprises:

generating a test current related to a current at said output of said video circuit; and

setting said logic level signal to a first state if said test current is above a threshold level, or setting said logic level signal to a second state if said test current is below said threshold level.

24. A method for configuring a video circuit into a relatively low power consumption mode and a relatively high power consumption mode, comprising:

detecting whether an input video signal is present at an input of said video circuit; and

configuring said video circuit into said relatively high power consumption mode if said input video signal is present at said input of said video circuit, or configuring said video circuit into said relatively low power consumption mode if said input video signal is not present at said input of said video circuit.

25. A method for configuring a video circuit into a relatively low power consumption mode and a relatively high power consumption mode, comprising:

electronically detecting whether a load is connected to an output of said video circuit; and

configuring said video circuit into said relatively high power consumption mode if said load is connected to said output of said video circuit, or configuring said video circuit into said relatively low power consumption mode if said output load is not connected to said output of said video circuit.