Voltage hold circuit and clock synchronization circuit

• US 20060220694A1
• Filed: 03/30/2006
• Published: 10/05/2006
• Est. Priority Date: 03/30/2005
• Status: Active Grant

• Current Assignee: Kyocera Corporation
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Watanabe, Kazuhiko
• Granted Patent: US 7,332,940 B2
• Time in Patent Office: Days
• US Class Current: 327/94
• CPC Class Codes: H03L 7/148 said digital means comprising a counter or a divider

Abstract

A voltage hold circuit which holds an input signal voltage includes a voltage comparator unit configured to output a result of comparison between a voltage of an externally inputted control signal and a voltage of an outputted analog hold signal, a digital value hold unit configured to increase or decrease a hold value which is a digital value it holds, based on the comparison result, and to output a digital hold signal which is a digital value generated based on the hold value, and a D/A converter unit configured to convert the digital hold signal to an analog value for output as the analog hold signal.

Claims

1. A voltage hold circuit which holds a voltage of an external input signal, comprising:

a voltage comparator unit configured to output a result of comparison between a voltage of an externally inputted control signal and a voltage of an analog hold signal outputted from the voltage hold circuit;

a digital value hold unit configured to increase or decrease a hold value which is a digital value held by the digital value hold unit, based on the comparison result, and to output a digital hold signal which is a digital value generated based on the hold value; and

a D/A converter unit configured to convert the digital hold signal to an analog value for output as the analog hold signal.

2. The voltage hold circuit as set forth in claim 1, wherein the digital value hold unit is configured to increase the hold value held by the digital value hold unit when the comparison result shows that the voltage of the control signal is higher than the voltage of the analog hold signal, and to decrease the hold value held by the digital value hold unit when the comparison result shows that the voltage of the control signal is lower than the voltage of the analog hold signal.

3. The voltage hold circuit as set forth in claim 1, wherein the digital value hold unit is configured to output an average value of hold values in a certain past period as the digital hold signal.

4. The voltage hold circuit as set forth in claim 1, wherein the digital value hold unit is configured to adjust an amount by which the hold value is increased or decreased, based on results of comparison by the voltage comparator unit in a certain past period.

5. The voltage hold circuit as set forth in claim 1, wherein:

the voltage comparator unit is a comparator; and

the digital value hold unit is a counter.

6. A clock synchronization circuit, comprising:

an oscillator configured to control a frequency of an output clock signal to be outputted, based on a voltage of an input signal;

a phase comparator configured to output a phase difference between an externally inputted reference clock signal and a comparison clock signal generated based on the output clock signal and being of a frequency equal to a frequency of the reference clock signal;

a low-pass filter configured to remove an alternating-current component from an output of the phase comparator for conversion to a control signal which is a direct-current signal;

a voltage hold circuit configured to hold a voltage of the control signal; and

a switch configured to obtain the control signal and an analog hold signal outputted from the voltage hold circuit, and to input the analog hold signal to the oscillator when obtaining an alarm signal showing that a reliable reference clock signal is not inputted, and to input the control signal to the oscillator when not obtaining the alarm signal;

the voltage hold circuit comprising;

a voltage comparator unit configured to output a result of comparison between the voltage of the control signal and a voltage of the analog hold signal;

a digital value hold unit configured to increase or decrease a hold value which is a digital value held by the digital value hold unit, based on the comparison result, and to output a digital hold signal which is a digital value generated based on the hold value; and

a D/A converter unit configured to convert the digital hold signal to an analog value for output as the analog hold signal.