High-speed, low-power input buffer for integrated circuit devices

• US 20060220704A1
• Filed: 03/29/2005
• Published: 10/05/2006
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Promos Technologies Pte Limited Singapore
• Inventors: Butler, Douglas Blaine
• Granted Patent: US 7,250,795 B2
• Time in Patent Office: Days
• US Class Current: 327/112
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Claims

1. An integrated circuit device including at least one input buffer comprising:

a pull-up device operatively coupled to a first voltage node;

a pull-down device operatively coupled between said pull-up device and a second voltage node, said pull-up and pull-down devices being capacitively coupled to an input voltage signal;

means for inducing a voltage offset between said input voltage signal and said pull-up device;

means for inducing a voltage offset between said input voltage signal and said pull-down device; and

an output node intermediate said pull-up and pull-down devices.

2. The integrated circuit device of claim 1 wherein said pull-up and pull-down devices comprise MOS transistors.

3. The integrated circuit device of claim 2 wherein said pull-up device comprises a P-channel transistor and said pull-down device comprises an N-channel transistor.

4. The integrated circuit device of claim 1 wherein said first voltage node comprises a supply voltage source and said second voltage node comprises circuit ground.

5. The integrated circuit device of claim 1 wherein said pull-down device is operatively coupled to said second voltage node through a first switching device in response to a first calibration signal.

6. The integrated circuit device of claim 5 further comprising:

a second switching device for selectively applying said input voltage signal to said pull-up and pull-down devices in response to a second calibration signal.

7. The integrated circuit device of claim 6 further comprising:

a third switching device for selectively applying a reference voltage signal to said pull-up and pull-down devices in response to a third calibration signal.

8. The integrated circuit device of claim 7 further comprising:

a fourth switching device for selectively coupling said output node to said second voltage node in response to a fourth calibration signal.

9. The integrated circuit device of claim 8 further comprising:

a resistive element coupling said fourth switching device to said second voltage node.

10. The integrated circuit device of claim 8 further comprising:

fifth and sixth switching devices for selectively coupling said reference voltage signal to said output node in response to respective fifth and sixth calibration signals.

11. The integrated circuit device of claim 7 wherein said second and third calibration signals are complementary.

12. The integrated circuit device of claim 8 wherein said first and fourth calibration signals are complementary.

13. The integrated circuit device of claim 10 wherein said fifth and sixth calibration signals are complementary.

14. The integrated circuit device of claim 1 further comprising:

an inverter for coupling said output node to an output terminal of said input buffer.

15. The integrated circuit device of claim 1 comprising at least two of said input buffers associated with at least one pin of said integrated circuit device.

16. The integrated circuit device of claim 15 wherein said at least two of said input buffers are alternatively coupled to receive said input voltage signal and to provide an output voltage signal during a respective operational phase thereof.

17. An integrated circuit input buffer comprising:

an input terminal for receiving an input voltage signal;

an output terminal for providing an output voltage signal in response to said input voltage signal when said input buffer is in an operational phase thereof; and

a reference voltage terminal for providing a reference voltage signal to said input buffer while said input buffer is in an alternative calibration phase of operation.

18. The integrated circuit input buffer of claim 17 wherein said reference voltage terminal is coupled to said input buffer in response to a first calibration signal.

19. The integrated circuit input buffer of claim 17 wherein said input terminal is coupled to said input buffer in response to a second complementary calibration signal.

20. A method for operating an input buffer for an integrated circuit device having input and reference voltage inputs thereto, said method comprising:

providing a first level of through current to an output node of said input buffer when a first voltage on said input voltage input is substantially equal to a second voltage on said reference voltage input; and

providing a second lesser level of through current to said output node when said first voltage is not substantially equal to said second voltage.

21. An integrated circuit device comprising:

at least two input buffers coupled to at least one input pin of said integrated circuit device.

22. The integrated circuit device of claim 21 wherein said at least two input buffers are alternatively in operational and calibration phases of operation.