Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells

• US 20060221705A1
• Filed: 12/06/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Hemink, Gerrit Jan, Kamei, Teruhiko
• Granted Patent: US 7,486,564 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3472 Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.

Claims

1. A method of soft programming non-volatile memory, comprising:

applying one or more soft programming pulses to a set of non-volatile storage elements until said set is verified as soft programmed;

inhibiting soft programming of a first subset of said set of non-volatile storage elements after said set is verified as soft programmed; and

applying one or more additional soft programming pulses to a second subset of said set of non-volatile storage elements while inhibiting soft programming of said first subset.

2. The method of claim 1, further comprising:

verifying whether said set of non-volatile storage elements is soft programmed in between applying each of said one or more soft programming pulses.

3. The method of claim 2, wherein:

verifying whether said set of non-volatile storage elements is soft programmed includes verifying whether said first subset of non-volatile storage elements is soft programmed while excluding said second subset of non-volatile storage elements from verification.

4. The method of claim 3, wherein:

verifying whether said first subset is soft programmed includes applying an erase verify voltage to each non-volatile storage element in said first subset; and

excluding said second subset from verification includes applying a voltage larger than said erase verify voltage to each non-volatile storage element in said second subset.

5. The method of claim 1, further comprising:

verifying whether said second subset of non-volatile storage elements is soft programmed in between applying each of said one or more additional soft programming pulses; and

wherein said applying one or more additional soft programming pulses includes applying said one or more additional soft programming pulses until said second subset is verified as soft programmed.

6. The method of claim 5, wherein:

verifying whether said second subset is soft programmed includes verifying that said second subset is soft programmed when at least one non-volatile storage element of said second subset reaches a verify level.

7. The method of claim 5, wherein:

verifying whether said second subset is soft programmed includes excluding said first subset of non-volatile storage elements from verification.

8. The method of claim 7, wherein:

verifying whether said second subset is soft programmed includes applying an erase verify voltage to each non-volatile storage of said second subset; and

excluding said first subset from verification includes applying a voltage larger than said erase verify voltage to each non-volatile storage element in said first subset.

9. The method of claim 1, wherein:

applying said one or more soft programming pulses includes increasing a size of said one or more soft programming pulses by a first step size in between applying each of said one or more soft programming pulses.

10. The method of claim 9, wherein:

applying said one or more additional soft programming pulses includes increasing a size of said one or more additional soft programming pulses by a second step size in between applying each of said one or more additional soft programming pulses.

11. The method of claim 10, wherein:

said one or more soft programming pulses includes a last soft programming pulse applied to said set before said set is verified as successfully soft programmed; and

said applying said one or more additional soft programming pulses includes, before applying a first of said one or more additional soft programming pulses, increasing a size of said last soft programming pulse by a third step size for said first of said one or more additional soft programming pulses.

12. The method of claim 11, wherein:

said first step size and said second step size are a same step size.

13. The method of claim 1, wherein said applying said one or more soft programming pulses includes:

decreasing a size of said one or more soft programming pulses by a first step size after applying a first soft programming pulse if said set is not verified as soft programmed after application of said first soft programming pulse; and

increasing said size of said one or more soft programming pulses by a second step size after applying a second soft programming pulse if said set is not verified as soft programmed after application of said second soft programming pulse.

14. The method of claim 13, wherein said applying said one or more additional soft programming pulses includes:

in between applying each of said one or more additional soft programming pulses, increasing a size of said one or more additional soft programming pulses by a third step size.

15. The method of claim 14, wherein:

said one or more soft programming pulses includes a last soft programming pulse applied to said set before said set is verified as successfully soft programmed; and

said applying said one or more additional soft programming pulses includes, before applying a first of said one or more additional soft programming pulses, increasing a size of said last soft programming pulse by a fourth step size for said first of said one or more additional soft programming pulses.

16. The method of claim 15, wherein:

said second step size and said third step size are a same size.

17. The method of claim 1, wherein:

said first subset of non-volatile storage elements are interior non-volatile storage elements of said set; and

said second subset of non-volatile storage elements are end non-volatile storage elements of said set.

18. The method of claim 17, wherein:

said second subset includes a first non-volatile storage element adjacent to a first select gate for said set and a second non-volatile storage element adjacent to a second select gate for said set.

19. The method of claim 18, wherein:

said second subset further includes a third non-volatile storage element adjacent to said first non-volatile storage element and a fourth non-volatile storage element adjacent to said second non-volatile storage element.

20. The method of claim 1, wherein:

said set of non-volatile storage elements is a NAND string.

21. The method of claim 1, wherein:

said set of non-volatile storage elements is a set of multi-state flash memory devices.

22. A method of soft programming non-volatile memory, comprising:

applying a soft programming voltage to each non-volatile storage element in a set of non-volatile storage elements;

verifying whether said set of non-volatile storage elements is soft programmed;

repeating said applying and verifying until said set of non-volatile storage elements is verified as soft programmed;

applying said soft programming voltage to each non-volatile storage element in a subset of said set of non-volatile storage elements after verifying that said set of non-volatile storage elements is soft programmed; and

verifying whether said subset of non-volatile storage elements is soft programmed.

23. The method of claim 22, wherein:

said subset is a first subset of said set of non-volatile storage elements;

said set includes a second subset of non-volatile storage elements;

said verifying whether said first subset is soft programmed includes excluding said second subset of non-volatile storage elements from verification.

24. The method of claim 23, wherein:

verifying whether said set of non-volatile storage elements is soft programmed includes verifying whether said second subset of non-volatile storage elements is soft programmed while excluding said first subset of non-volatile storage elements from verification.

25. The method of claim 22, wherein:

repeating said applying and verifying includes increasing a size of said soft programming voltage by a first step size prior to reapplying to said set; and

applying said soft programming voltage to each non-volatile storage element in said subset includes increasing said size of said soft programming voltage by a second step size prior to first applying to said subset after said set has been verified as soft programmed.

26. The method of claim 22, wherein said repeating includes:

after a first application of said soft programming voltage to said set, decreasing a size of said soft programming voltage by a first step size; and

after a second application of said soft programming voltage to said set and thereafter, increasing a size of said soft programming voltage by a second step size.

27. The method of claim 22, wherein:

said set of non-volatile storage elements is a NAND string of multi-state flash memory devices.

28. A method of soft programming non-volatile memory, comprising:

applying one or more soft programming pulses to a plurality of sets of non-volatile storage elements, said one or more soft programming pulses are applied until said plurality of sets of non-volatile storage elements is verified as soft programmed;

inhibiting soft programming of a first subset of non-volatile storage elements in each set of non-volatile storage elements after said plurality of sets is verified as soft programmed; and

applying one or more additional soft programming pulses to a second subset of non-volatile storage elements in each set of non-volatile storage elements while inhibiting soft programming of said first subset in each set.

32. The method of claim 28, further comprising:

verifying whether said second subsets of non-volatile storage elements in each set are soft programmed in between applying each of said one or more additional soft programming pulses, said second subsets are verified as soft programmed when a pre-determined number of said second subsets are verified as soft programmed; and

wherein said applying one or more additional soft programming pulses includes applying said one or more additional soft programming pulses until said predetermined number of said second subsets are verified as soft programmed.

33. The method of claim 32, wherein:

verifying whether said second subsets of each set are soft programmed includes excluding said first subsets of each set from verification.

34. The method of claim 28, wherein:

applying said one or more soft programming pulses includes increasing a size of said one or more soft programming pulses by a first step size in between applying each of said one or more soft programming pulses; and

applying said one or more additional soft programming pulses includes increasing a size of said one or more additional soft programming pulses by a second step size in between applying each of said one or more additional soft programming pulses.

35. The method of claim 28, wherein said applying said one or more soft programming pulses includes:

decreasing a size of said one or more soft programming pulses by a first step size after applying a first soft programming pulse if said plurality of sets is not verified as soft programmed after application of said first soft programming pulse; and

increasing said size of said one or more soft programming pulses by a second step size after applying a second soft programming pulse if said plurality of sets is not verified as soft programmed after application of said second soft programming pulse.

36. The method of claim 28, wherein:

said set of non-volatile storage elements is a NAND string of multi-state flash memory devices.

29. The method of 28, further comprising:

verifying whether said plurality of sets of non-volatile storage elements is soft programmed in between applying each of said one or more soft programming pulses.

30. The method of claim 29, wherein:

said plurality of sets of non-volatile storage elements is verified as soft programmed when a pre-determined number of said plurality of sets are verified as soft programmed.

31. The method of claim 29, wherein:

verifying whether said plurality of sets of non-volatile storage elements is soft programmed includes verifying whether said first subsets of non-volatile storage elements in each set are soft programmed while excluding said second subsets of non-volatile storage elements in each set from verification.

37. A method of soft programming non-volatile memory, comprising:

applying one or more soft programming pulses to each non-volatile storage element in a plurality of NAND strings;

verifying soft programming of said plurality of NAND strings;

repeating said applying and verifying until a predetermined number of said plurality of NAND strings are verified as soft programmed;

inhibiting soft programming of a first subset of non-volatile storage elements in each NAND string; and

applying one or more additional soft programming pulses to a second subset of non-volatile storage elements in each NAND string after said predetermined number of NAND strings are verified as soft programmed.

38. The method of claim 37, further comprising:

verifying whether said second subsets of non-volatile storage elements in each NAND string are soft programmed in between applying each of said one or more additional soft programming pulses; and

wherein said applying one or more additional soft programming pulses includes applying said one or more additional soft programming pulses until said second subsets of non-volatile storage elements in each set are verified as soft programmed.

39. The method of claim 38, wherein:

verifying whether said second subsets of each set are soft programmed includes excluding said first subsets of each set from verification.

40. The method of claim 37, wherein:

applying one or more soft programming pulses includes increasing a size of said one or more soft programming pulses by a first step size in between applying each of said one or more soft programming pulses; and

applying said one or more additional soft programming pulses includes increasing a size of said one or more additional soft programming pulses by a second step size in between applying each of said one or more additional soft programming pulses.

41. The method of claim 37, wherein said applying said one or more soft programming pulses includes:

decreasing a size of said one or more soft programming pulses by a first step size after applying a first soft programming pulse if said predetermined number of said plurality of NAND strings are not verified as soft programmed after application of said first soft programming pulse; and

increasing said size of said one or more soft programming pulses by a second step size after applying a second soft programming pulse if said predetermined number of said plurality of NAND strings are not verified as soft programmed after application of said second soft programming pulse.

42. A method of soft programming non-volatile memory, comprising:

programming each non-volatile storage element in a set of non-volatile storage elements until said set is verified as having reached a target level;

stopping programming of each non-volatile storage element in a first subset of said set of non-volatile storage elements after said set is verified as having reached said target level; and

continuing to program each non-volatile storage element in a second subset of said set of non-volatile storage elements after stopping programming of each non-volatile storage element in said first subset.

43. The method of claim 42, further comprising:

verifying whether said second subset of non-volatile storage elements has reached said target level, said verifying includes excluding said first subset of non-volatile storage elements from verification; and

wherein said continuing to program each non-volatile storage element in said second subset continues until said second subset is verified as having reached said target level.

44. The method of claim 42, wherein:

said programming includes applying one or more soft programming pulses; and

said target level is a soft programming target level.

45. The method of claim 42, wherein:

said set of non-volatile storage elements includes a plurality of NAND strings;

said set is verified as having reached said target level when a predetermined number of said plurality of NAND strings are determined to include at least one non-volatile storage element that has reached said target level.

46. The method of claim 42 wherein:

said set of non-volatile storage elements is a set of multi-state flash memory devices.