Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells

• US 20060221709A1
• Filed: 12/06/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Hemink, Gerrit Jan, Kamei, Teruhiko
• Granted Patent: US 7,400,537 B2
• Time in Patent Office: Days
• US Class Current: 365/185.290
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3472 Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.

Claims

1. A non-volatile memory system, comprising:

a set of non-volatile storage elements, said set includes a first subset and a second subset of non-volatile storage elements; and

managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry erases said set by;

enabling erasing of said first and said second subset of non-volatile storage elements,

applying one or more erase voltage pulses to said set while said first and second subset are enabled for erasing until said first subset is verified as erased,

after said first subset is verified as erased, inhibiting said first subset from further erasing while enabling erasing of said second subset, and

applying one or more additional erase voltage pulses to said set while said first subset is inhibited and said second subset in enabled until said second subset is verified as erased.

2. The non-volatile memory system of claim 1, wherein said managing circuitry, subsequent to erasing said set of non-volatile storage elements, soft-programs said set of non-volatile storage elements by:

applying one or more soft programming pulses to said set of non-volatile storage until said set is verified as soft programmed;

inhibiting soft programming of said first subset of said set of non-volatile storage elements after said set is verified as soft programmed; and

applying one or more additional soft programming pulses to said second subset of said set of non-volatile storage elements while inhibiting soft programming of said first subset.

3. The non-volatile memory system of claim 2, wherein said managing circuitry:

verifies whether said second subset is soft programmed in between applying each of said one or more additional soft programming pulses, said verifying includes excluding said first subset from verification.

4. The non-volatile memory system of claim 1, wherein said managing circuitry verifies, in between applying each of said one or more erase voltage pulses, whether said first subset of non-volatile storage elements is erased, said managing circuitry excludes said second subset of non-volatile storage elements from verification when verifying whether said first subset is erased.

5. The non-volatile memory system of claim 4, wherein said managing circuitry verifies by applying an erase verify voltage to said first subset and a voltage larger than said erase verify voltage to said second subset in order to verify said first subset while excluding said second subset from verification.

6. The non-volatile memory system of claim 1, wherein said managing circuitry verifies, in between applying each of said one or more additional erase voltage pulses, whether said second subset of non-volatile storage elements is erased.

7. The non-volatile memory system of claim 6, wherein said managing circuitry excludes said first subset of non-volatile storage elements from verification when verifying whether said second subset is erased.

8. The non-volatile memory system of claim 1, wherein said applying said one or more erase voltage pulses includes:

decreasing a size of said one or more erase voltage pulses by a first step size after applying a first erase voltage pulse if said first subset is not verified as erased; and

increasing said size of said one or more erase voltage pulses by a second step size after applying a second erase voltage pulse if said first subset is not verified as erased.

9. The non-volatile memory system of claim 8, wherein said applying said one or more additional erase voltage pulses includes:

in between applying each of said one or more additional erase voltage pulses, incrementing a size of said one or more additional erase voltage pulses by a third step size.

10. The non-volatile memory system of claim 9, wherein:

said one or more erase voltage pulses includes a last erase voltage pulse applied to said set before said first subset is verified as successfully erased;

said applying said one or more additional erase voltage pulses includes, before applying a first of said one or more additional erase voltage pulses, incrementing said last erase voltage pulse by a fourth step size for said first of said one or more additional erase voltage pulses.

11. The non-volatile memory system of claim 10, wherein:

said second step size and said third step size are a same size.

12. The non-volatile memory system of claim 1, wherein:

said first subset of non-volatile storage elements are interior non-volatile storage elements of said set; and

said second subset of non-volatile storage elements are end non-volatile storage elements of said set.

13. The non-volatile memory system of claim 12, wherein:

said second subset includes a first non-volatile storage element adjacent to a first select gate for said set and a second non-volatile storage element adjacent to a second select gate for said set.

14. The non-volatile memory system of claim 13, wherein:

said second subset further includes a third non-volatile storage element adjacent to said first non-volatile storage element and a fourth non-volatile storage element adjacent to said second non-volatile storage element.

15. The non-volatile memory system of claim 1, wherein:

said set of non-volatile storage elements is a set of multi-state flash memory devices.

16. The non-volatile memory system of claim 1, wherein:

said set of non-volatile storage elements is a NAND string.

17. The non-volatile memory system of claim 1, wherein:

said managing circuitry includes at least one of a controller, a state machine, and a row controller.

18. A non-volatile memory system, comprising:

a set of non-volatile storage elements, said set includes a first subset and a second subset of non-volatile storage elements; and

managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry erases said set by applying an erase voltage to said set while each non-volatile storage element in said set is enabled for erase and verifying whether said first subset is erased while excluding said second subset from verification, said managing circuitry repeats said applying and verifying until said first subset is verified as erased, said managing circuitry inhibits erasing of said first subset and enables erasing of said second subset after said first subset is verified as erased and applies an erase voltage to said set while said second subset is enabled for erase and said first subset is inhibited from erase, said managing circuitry verifies whether said set of non-volatile storage elements is erased by verifying whether said second subset is erased.

19. The non-volatile memory system of claim 18, wherein said managing circuitry soft-programs said set of non-volatile storage elements subsequent to erasing said set of non-volatile storage elements by:

applying a soft programming voltage to each non-volatile storage element in said set;

verifying whether said set is soft programmed;

repeating said applying and verifying until said set is verified as soft programmed;

applying said soft programming voltage to each non-volatile storage element in said second subset after verifying that said set is soft programmed; and

verifying whether said second subset is soft programmed.

20. The non-volatile memory system of claim 19, wherein:

verifying whether said second subset of non-volatile storage elements is soft programmed includes excluding said first subset of non-volatile storage elements from verification.

21. The non-volatile memory system of claim 18, wherein said managing circuitry verifies whether said set of non-volatile storage elements is erased while excluding said first subset from verification.

22. The non-volatile memory system of claim 18, wherein said managing circuitry verifies whether said set of non-volatile storage elements is erased by verifying whether said first subset and said second subset are erased.

23. The non-volatile memory system of claim 18, wherein:

said managing circuitry increases a size of said erase voltage by a first step size as part of repeating said applying and verifying; and

said managing circuitry repeats application of said erase voltage to said set while said second subset is enabled for erase and said first subset is inhibited from erase until said second subset is verified as erased, said managing circuitry increases a size of said erase voltage by a second step size before reapplying said erase voltage to said set while said second subset is enabled for erase and said first subset is inhibited from erase.

24. The non-volatile memory system of claim 23, wherein:

said first and second step size are a same step size.

25. A non-volatile memory system, comprising:

a set of non-volatile storage elements, said set includes a first subset and a second subset of non-volatile storage elements; and

managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry receives a request to erase said set of non-volatile storage elements, said managing circuitry erases said set in response to said request by;

applying an erase voltage to said set while enabling erasure of each non-volatile storage element of the set,

verifying whether said first subset of non-volatile storage elements is erased,

repeating said applying and verifying until said first subset is verified as erased,

inhibiting erasing of said first subset of non-volatile storage elements subsequent to said repeating,

applying an erase voltage to said set while said first subset is inhibited in order to further erase said second subset, and

verifying whether said set of elements is erased by verifying whether said second subset of elements is erased.

26. The non-volatile memory system of claim 25, wherein said managing circuitry, subsequent to erasing said set of non-volatile storage elements, soft-programs said set of non-volatile storage elements by:

applying a soft programming voltage to each non-volatile storage element in said set;

verifying whether said set is soft programmed;

repeating said applying and verifying until said set is verified as soft programmed;

applying said soft programming voltage to each non-volatile storage element in said second subset after verifying that said set is soft programmed; and

verifying whether said second subset is soft programmed.

27. The non-volatile memory system of claim 25, wherein verifying whether said first subset is erased includes excluding said second subset from verification.

28. The non-volatile memory system of claim 25, wherein:

repeating said applying and verifying includes increasing a size of said erase voltage by a first step size prior to reapplying to said set; and

applying an erase voltage to said set while said first subset is inhibited from further erase includes increasing said size of said erase voltage by a second step size prior to first applying said erase voltage to said set after said first subset has been verified as erased.