Semiconductor memory card, semiconductor memory control apparatus, and semiconductor memory control method

• US 20060221719A1
• Filed: 09/13/2004
• Published: 10/05/2006
• Est. Priority Date: 09/18/2003
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Maeda, Takuji, Gotoh, Yoshiho, Horiuchi, Koichi, Ohara, Jun, Inoue, Shinji, Inoue, Manabu, Nakanishi, Masahiro, Izumi, Tomoaki, Kasahara, Tetsushi, Tamura, Kazuaki, Matsuno, Kiminori, Tsujita, Shoichi
• Granted Patent: US 7,654,466 B2
• Time in Patent Office: Days
• US Class Current: 365/189.50
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A host information memory is provided in a semiconductor memory card and a data write start address and a data size supplied by an access unit are stored. A free physical area generation section determines whether or not to perform erasing of an invalid block of a nonvolatile memory when writing of data based on the data write start address and data size, and determines the number of blocks to be erased. When erasing, writing of data and erasing of invalid blocks are simultaneously performed with respect to different memory chips. Erase process of data, herewith, can be optimized and high speed access from the access unit to a semiconductor memory card can be realized.

Claims

1-11. -11. (canceled)

12. A semiconductor memory card used by being connected to an access unit, comprising:

a host interface section which sends a control signal and data to said access unit and receives a signal from said access unit;

a nonvolatile memory which includes a plurality of nonvolatile memory chips and in which a plurality of continuous sectors is grouped to be a block as a minimum unit of data erasing;

a memory controller which is connected to each of said plurality of nonvolatile memory chips with respectively independent bidirectional buses and controls erasing, writing, and reading of data; and

a host information memory which temporarily stores a write speed mode given by said access unit, wherein

said memory controller includes a nonvolatile memory access section which performs writing with respect to said plurality of nonvolatile memory chips with controlling write timing to each of said plurality of nonvolatile memories depending on a speed mode stored in said host information memory.

13. The semiconductor memory card according to claim 12, wherein said memory controller performs, in parallel, writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is a high speed mode, and sequentially performs writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is a low speed mode.

14. A semiconductor memory control apparatus used by being connected to a nonvolatile memory which includes a plurality of nonvolatile memory chips in which a plurality of continuous sectors is grouped to be a block as a minimum unit of data erasing:

a host interface section which sends a control signal and data to an access unit and receives a signal from said access unit;

a memory controller which is connected to each of said plurality of nonvolatile memory chips with respectively independent bidirectional buses and controls erasing, writing, and reading of data; and

a host information memory which temporarily stores a write speed mode given by said access unit, wherein

said memory controller includes a nonvolatile memory access section which performs writing with respect to said plurality of nonvolatile memory chips with controlling write timing to each of said plurality of nonvolatile memories depending on the speed mode stored in said host information memory.

15. The semiconductor memory control apparatus according to claim 14, wherein said memory controller performs, in parallel, writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is a high speed mode, and sequentially performs writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is at a low speed mode.

16. A semiconductor memory control method in a semiconductor memory card having a nonvolatile memory which includes a plurality of nonvolatile memory chips and in which a plurality of continuous sectors is grouped to be a block as a minimum unit of data erasing and a host information memory for temporarily storing a write speed mode given by an access unit, said semiconductor memory control method comprising the step of:

performing writing with respect to said plurality of nonvolatile memory chips with controlling write timing to each of said plurality of nonvolatile memories depending on the speed mode stored in said host information memory.

17. The semiconductor memory control method according to claim 16, further comprising the steps of:

performing, in parallel, writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is a high speed mode, and

sequentially performing writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is a low speed mode.

18-23. -23. (canceled)