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Method and apparatus for incorporating block redundancy in a memory array

  • US 20060221728A1
  • Filed: 03/31/2005
  • Published: 10/05/2006
  • Est. Priority Date: 03/31/2005
  • Status: Active Grant
First Claim
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1. A method for implementing block redundancy in an integrated circuit memory array, said method comprising:

  • mapping the array lines of a defective block of a first type into a spare block of the same type;

    mapping array lines of a first adjacent block which are shared with array lines of the defective block, and mapping array lines of a second adjacent block which are shared with array lines of the defective block, into a second spare block of a second type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.

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