Multi-port memory device

• US 20060221757A1
• Filed: 12/30/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Kyung-Whan
• Granted Patent: US 7,283,420 B2
• Time in Patent Office: Days
• US Class Current: 365/230.50
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

The present invention proposes a multi-port memory device for preventing a degradation of a global data drive efficiency by turning off the switches which do not discharge a global data bus. The multi-port memory device includes a global data bus containing a plurality of bus lines; a plurality of banks including a transmitter and a receiver for exchanging a data with the global data bus; a plurality of ports including the transmitter and the receiver; a plurality of switches for selectively connecting the transmitter and the receiver with the global data bus; and a switching controller for generating a switch signal in response to a drive pulse and a data signal inputted to the transmitter, wherein the switch signal turns off the switches corresponding to the banks which are not discharging the global data bus.

Claims

1. A multi-port memory device, comprising:

a global data bus;

a plurality of banks, each including a transmitter and a receiver, the transmitter and the receiver for each bank exchanging a data with the global data bus;

a plurality of ports, each including a transmitter and a receiver;

a plurality of switches, each provided between the transmitter and the receiver in each bank and the global data bus for selectively connecting the transmitter of the bank and the corresponding receiver of the global data bus; and

a switching controller for generating a switch signal for each of the switches in response to a drive pulse and a data signal at the input of the transmitter of the bank,

wherein the switch signal turns on/off the switches corresponding to the banks and when a switch corresponding to a bank is turned off, the transmitter of the bank does not discharge the global data bus.

2. The multi-port memory device as recited in claim 1, wherein each of the transmitters includes first and second NMOS transistors serially connected to each other between the global data bus and a ground voltage, the first and the second NMOS transistors respectively receiving the drive pulse and the data signal through their corresponding gates.

3. The multi-port memory device as recited in claim 2, wherein each of the receivers includes:

a first PMOS transistor whose first terminal is connected to a power voltage and whose second terminal and gate are diode-connected with each other;

a second PMOS transistor whose first terminal is connected to the power voltage and whose second terminal is connected to an output terminal;

a third NMOS transistor whose first terminal is connected to the second terminal of the first PMOS transistor, whose second terminal is connected to the global data bus, and whose gate receives a reference voltage;

a fourth NMOS transistor whose first terminal is connected to the output terminal and whose gate receives the reference voltage; and

a fifth NMOS transistor whose first terminal is connected to a second terminal of the fourth NMOS transistor, whose second terminal is connected to the ground voltage, and whose gate receives an evaluation signal.

4. A multi-port memory device, comprising:

a global data bus;

a plurality of banks, each including a transmitter and a receiver, the transmitter and the receiver exchanging data with the global data bus;

a plurality of ports, each including a transmitter and a receiver;

a plurality of switches, each provided between the transmitter and the receiver in each of the banks and the global data bus for selectively connecting the transmitter and the receiver with the global data bus;

a discharge signal generator for generating a discharge signal corresponding to each of the banks in response to a drive pulse and a data signal corresponding to each of the banks; and

a switch signal generator for generating a switch signal based on the discharge signal, wherein the switch signal turns on/off the switches corresponding to the banks and when the switch signal turns off a switch of a corresponding bank, the transmitter of the bank does not discharge the global data bus.

5. The multi-port memory device as recited in claim 4, wherein each of the transmitters includes first and second NMOS transistors serially connected with each other between the global data bus and a ground voltage, the first and the second NMOS transistors respectively receiving the drive pulse and the data signal through their corresponding gates.

6. The multi-port memory device as recited in claim 5, wherein each of the receivers includes:

a first PMOS transistor whose first terminal is connected to a power voltage and whose second terminal and gate are diode-connected each other;

a second PMOS transistor whose first terminal is connected to the power voltage and whose second terminal is connected to an output terminal;

a third NMOS transistor whose first terminal is connected to the second terminal of the first PMOS transistor, whose second terminal is connected to the global data bus, and whose gate receives a reference voltage;

a fourth NMOS transistor whose first terminal is connected to the output terminal and whose gate receives the reference voltage; and

a fifth NMOS transistor whose first terminal is connected to a second terminal of the fourth NMOS transistor, whose second terminal is connected to the ground voltage, and whose gate receives an evaluation signal.

7. The multi-port memory device as recited in claim 6, wherein each of the switches includes an NMOS transistor connected between each of the banks and the global data bus and receives the switch signal through gate.

8. The multi-port memory device as recited in claim 7, wherein the discharge signal generator comprises a plurality of NAND gates receiving the drive pulse and the data signal corresponding to each of the banks to thereby output the discharge signal.

9. The multi-port memory device as recited in claim 8, wherein the switch signal generator associated with a bank compromises a plurality of AND gates for logically combining the discharge signals except one corresponding to the bank to thereby output the switch signal.

10. The multi-port memory device as recited in claim 9, wherein each of the AND gates includes:

an NAND gate receiving the discharge signals except the one corresponding to the bank; and

an inverter for inverting an output from the NAND gate to thereby output the switch signal.