Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface

• US 20060222017A1
• Filed: 04/01/2005
• Published: 10/05/2006
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rahman, Mahibur, Quiroga, Emilio J.
• Granted Patent: US 7,936,793 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04J 3/0605 Special codes used as synchronising signal
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

Methods, devices and systems are provided for word synchronizing multiple serial data bitstreams (106) with a serial framing signal (106A). Offset values (420) are determined (512) from the relative locations of predetermined data correlation values (107) stored within the data buffers during a correlation mode to indicate the amount of skew observed between the framing channel and each of serial data channels. Data received during subsequent operation of each data stream is stored a buffer (402), and the framing signal (106A) is monitored to identify a boundary between data words. When a frame boundary occurs, parallel data is extracted from the buffer using the previously-stored offset values to compensate for bit skew between the data and framing channels.

Claims

1. A method for word synchronizing data received on a plurality of serial data channels to a framing signal received on a framing channel, the method comprising the steps of:

initially determining a plurality of offset values, each offset value indicating the amount of skew observed between the framing channel and one of the plurality of serial data channels;

storing the data received on each of the plurality of serial data channels in at least one buffer;

monitoring the framing signal to identify a frame boundary; and

extracting parallel data from the at least one buffer in response to the frame boundary, wherein the location of the parallel data within the at least one buffer is identified by the plurality of offset values.

2. The method of claim 1 wherein the step of initially determining the plurality of offset values comprises the steps of:

receiving correlation data on each of the plurality of serial data channels;

determining a data offset for each of the serial data channels; and

correlating the data offset for each of the serial data channels to a frame offset from the framing channel to thereby determine the offset value for each serial data channel.

3. The method of claim 2 wherein the step of initially determining the plurality of offset values further comprises the step of selecting the frame offset as the offset value when the data offset is a known value.

4. The method of claim 3 wherein the known value corresponds to a bit offset of zero.

5. The method of claim 2 wherein the correlation data comprises a repeated string of bits having pre-determined values.

6. The method of claim 5 further comprising the step of receiving the pre-determined string of bits before receiving the correlation data.

7. The method of claim 2 further comprising the step of entering a correlation mode prior to the determining step.

8. The method of claim 7 further comprising the step of ending the correlation mode after the determining step.

9. The method of claim 1 wherein the framing signal comprises a repeated string of bits having pre-determined values.

10. The method of claim 9 wherein the repeated string of bits is configured to repeat only at the frame boundary.

11. A device for word synchronizing a plurality of serial bitstreams in a multi-pin asynchronous interface, the plurality of serial bitstreams comprising a framing bitstream and a plurality of data bitstreams, the device comprising:

a plurality of buffers, each buffer corresponding to one of the serial bitstreams;

a plurality of word search modules each corresponding to one of the plurality of buffers, wherein each of the plurality of word search modules is configured to generate an offset signal identifying a location of a predetermined bit pattern in the corresponding buffer; and

a plurality of parallel word extraction modules, each of the plurality of parallel word extraction modules coupled to an associated one of the buffers and to an associated one of the word search modules each corresponding to one of the data bitstreams, and wherein each parallel word extraction module is configured to extract a parallel data word from the associated buffer using the data offset signal produced by the associated word search module in response to the offset signal produced by the word search module corresponding to the framing bitstream.

12. The device of claim 11 wherein the word search modules corresponding to each of the data bitstreams are further configured to receive an enable signal and to enter a correlation mode in response thereto.

13. The device of claim 11 wherein the word search modules corresponding to each of the data bitstreams are further configured receive a correlation word as the predetermined bit pattern.

14. The device of claim 11 wherein each of the plurality of buffers are maintained as shift registers.

15. The device of claim 14 further comprising a plurality of bit synchronization modules each associated with one of the serial bitstreams and configured to provide a phase strobe signal to the frame buffer.

16. The device of claim 14 further comprising a frame correlation reference sequencer configured to receive the phase strobe from the bit synchronization module associated with the framing bitstream and to sequentially indicate the state of the framing bitstream.

17. The device of claim 14 further comprising a plurality of data correlation reference sequencers each associated with one of the data bitstreams and coupled between the word search module and the parallel word extraction module corresponding to the associated data bitstream, each data correlation reference sequencer configured to receive the phase strobe signal from one of the bit synchronization modules and to sequentially indicate the state of the associated data bitstream.

18. A system for synchronizing a plurality of serial bitstreams having a common bitrate that are each received at a multi-pin asynchronous interface, the serial bitstreams comprising a framing bitstream and a plurality of data bitstreams, the system comprising:

a clock generator configured to produce a common clock signal having a frequency substantially equal to an integer multiple of the common bitrate;

a plurality of bit synchronization modules each associated with one of the plurality of serial bitstreams and configured to receive the common clock signal, and to bit synchronize the associated bitstream to the other serial bitstreams using the common clock signal; and

a word synchronization module configured to receive each of the bit synchronized bitstreams from the plurality of bit synchronization modules and to extract parallel data words therefrom, the word synchronization module comprising;

a plurality of buffers, each buffer corresponding to one of the synchronized bitstreams;

a plurality of word search modules each corresponding to one of the plurality of buffers, wherein each of the plurality of word search modules is configured to generate an offset signal identifying a location of a predetermined bit pattern in the corresponding buffer; and

a plurality of parallel word extraction modules, each of the plurality of parallel word extraction modules coupled to an associated one of the buffers and to an associated one of the word search modules each corresponding to one of the data bitstreams, and wherein each parallel word extraction module is configured to extract a parallel data word from the associated buffer using the data offset signal produced by the associated word search module in response to the offset signal produced by the word search module corresponding to the framing bitstream.

19. The system of claim 18 wherein each of the bit synchronization modules comprise:

an activity detection module configured to detect bit transitions occurring during each of a plurality of phases of the associated bitstream, each phase corresponding to a cycle of the common clock signal;

a phase selection module coupled to the activity detection module and configured to select one of the plurality of phases based upon the bit transitions detected within each of the plurality of phases; and

a phase extraction module coupled to the phase selection module, wherein the phase extraction module is configured to extract the selected phase of the associated bitstream to thereby bit synchronize the associated bitstream to the other serial bitstreams.

20. The system of claim 18 wherein the system is an interface between a radio frequency transceiver and a baseband modem.