Systems and methods for maintaining synchronicity during signal transmission

• US 20060222125A1
• Filed: 03/31/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Abandoned Application

• Current Assignee: Stratus Technologies Bermuda Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Stratus Technologies Bermuda Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: Wegner, Tim, Somers, Jeffrey, Edwards, John W. Jr.
• Application Number:
  US11/095,173
• Publication Number:
  US 20060222125A1
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H04L 7/00 Arrangements for synchronising receiver with transmitter synchronisation of generators of electric oscillations or pulses H03L7/00
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

Systems and methods are disclosed for facilitating synchronous communications over an asynchronous communications link. Specifically, embodiments of the present invention provide systems and methods for transmitting high-speed signals while maintaining lock-step determinism using remote clock phase adjustments. Embodiments of the present invention also provide systems and methods for maintaining determinism through the use of synchronized time slice counters within the various components.

Claims

1. A synchronized communications system comprising:

a transmitter comprising an embedded clock;

a receiver; and

an asynchronous communications link connecting the transmitter and the receiver;

wherein the transmitter is configured to establish an appropriate offset for the embedded clock in order to counteract the effect of a transmission delay between the transmitter and the receiver.

2. The system of claim 1, further comprising a round trip timer configured to measure the round trip time required to send a signal to the receiver over the communications link and to receive an acknowledgement back, the round trip time used to calculate the transmission delay.

3. The system of claim 1, wherein the transmitter and receiver are located within a fault tolerant computer system.

4. The system of claim 2, wherein the transmitter further comprises a transmitter clock.

5. The system of claim 4, wherein the round trip timer measures the round trip time relative to the transmitter clock.

6. The system of claim 5, wherein the signal comprises an embedded clock component and a data component, the embedded clock component based upon the embedded clock.

7. The system of claim 6, wherein the receiver is configured to use the embedded clock component to process the data component.

8. The system of claim 7, wherein after the offset has been established, the embedded clock is adjusted such that all future signals communicated between the transmitter and the receiver use the adjusted embedded clock.

9. A method for synchronizing a transmitter and a receiver, the transmitter having a transmitter clock and an embedded clock, the method comprising:

adding an offset to the embedded clock such that the transmitter and receiver operate in synchrony.

10. The method of claim 9, further comprising the step of calculating a transmission delay between the transmitter and receiver, such that the offset added to the embedded clock compensates for the transmission delay.

11. The method of claim 10, further comprising the step of transmitting a signal from the transmitter to the receiver containing an embedded clock signal, such that the receiver operates in lockstep with the transmitter through the use of the embedded clock signal.

12. The method of claim 11, wherein the transmitter and receiver are located within a fault-tolerant system.

13. A method for synchronizing a transmitter and a receiver through the use of a signal, the transmitter having a transmitter clock and an embedded clock, the receiver having a receiver clock, the method comprising:

(a) transmitting the signal from the transmitter to the receiver;

(b) transmitting an acknowledgement from the receiver to the transmitter;

(c) calculating and recording a round trip transit time defining the period between when the signal was sent by the transmitter and the acknowledgement was received by the transmitter;

(d) adding an offset to the embedded clock;

(e) repeating steps (a) through (d) until a stopping condition has been reached; and

(f) thereafter, selecting a preferred offset and adjusting the embedded clock accordingly.

14. The method of claim 13, wherein the signal comprises an embedded clock component and a data component, the embedded clock component based upon the embedded clock.

15. The method of claim 14, further comprising:

(g) after the embedded clock has been adjusted, transmitting all subsequent data components with adjusted embedded clock components based upon the adjusted embedded clock.

16. The method of claim 15, further comprising:

(h) using the adjusted embedded clock in the receiver to process the data component.

17. The method of claim 13, wherein the preferred offset is based upon the median round trip transit time.

18. The method of claim 13, wherein the preferred offset is based upon the average round trip transit time.

19. The method of claim 13, wherein the stopping condition comprises repeating steps (a) through (d) a predetermined number of times.

20. The method of claim 13, wherein the stopping condition comprises repeating steps (a) through (d) until the embedded clock has been measured for each possible phase of the transmit clock.

21. The method of claim 13, wherein, the step of adjusting the transmitter clock further comprises adjusting the phase of the embedded clock forward or backward with respect to the transmitter clock.

22. A synchronized communications system comprising:

a transmitter comprising a transmitter clock and a first time slice counter;

a receiver comprising a receiver clock, a buffer and a second time slice counter, each of the first and second time slice counters configured to periodically and synchronously produce a signal representing a time slice; and

an asynchronous communications link connecting the transmitter and the receiver;

wherein, the transmitter is configured such that it transmits data packets across the communications link only during a time slice.

23. The system of claim 22, wherein the buffer is configured to receive and store each packet sent across the communications link.

24. The system of claim 23, wherein the receiver is configured to obtain from the buffer and process each packet received only after the packet is declared valid.

25. The system of claim 24, wherein each packet is declared valid after the receiver waits a calculated number of time slices after the packet is first received such that the entire packet is received before it is processed.

26. The system of claim 22, wherein the transmitter and receiver are located within a fault tolerant computer system.

27. The system of claim 22, wherein the buffer comprises a FIFO buffer.

36. The system of claim 22, wherein the time slice is calculated to be a period of time greater than the link variance and also the least common denominator between a transmitter clock period and a receiver clock period.

37. The system of claim 36, wherein the link variance comprises a time difference between a maximum signal transmission time and a minimum signal transmission time to transmit from the transmitter to the receiver across the communications link.

28. A method for transmitting a signal from a transmitter to a receiver over an asynchronous communications link, the transmitter having a transmitter clock and the receiver having a receiver clock, the method comprising:

calculating the link variance across the communications link and;

transmitting the signal from the transmitter to the receiver across the communications link during a time slice.

29. The method of claim 28, further comprising the step of buffering the signal when it is received and processing the signal only at the beginning of the next time slice.

30. The method of claim 28, further comprising the step of buffering the signal when it is received and processing the signal only at the beginning of the time slice occurring after the entire signal has been buffered and declared valid.

31. The method of claim 30, further comprising the step of calculating the number of time slices required to receive the signal and declaring the signal valid after the calculated number of time slices have elapsed.

32. The method of claim 28, wherein calculating the link variance comprises determining the time difference between a maximum signal transmission time and a minimum signal transmission time to transmit from the transmitter to the receiver across the communications link.

33. The method of claim 28, wherein the time slice is programmable.

34. The method of claim 28, wherein the transmitter and receiver are located within a fault-tolerant computer system.

35. The method of claim 28, wherein the time slice is calculated to be a period of time greater than the link variance and also the least common denominator between a transmitter clock period and a receiver clock period.