Semiconductor device and method of manufacturing the same

• US 20060223253A1
• Filed: 04/04/2006
• Published: 10/05/2006
• Est. Priority Date: 04/05/2005
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Risaki, Tomomitsu
• Granted Patent: US 7,492,035 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Provided is a semiconductor device having a structure in which: a well region of a high resistance p-type semiconductor is disposed in a given depth from a surface of an n-type or p-type semiconductor substrate; a plurality of trenches extend from the surface of the well region to a certain depth; a gate insulating film is formed on a surface of a convex/concave portion on which the trenches are formed; a gate electrode is embedded into the trenches. The semiconductor device includes: a gate electrode film that is disposed on a substrate surface in contact with the gate electrode embedded into the trenches in the convexo-concave portion region except for a portion in the vicinity of both ends of the trenches; and a source region and a drain region that are two low resistance n-type semiconductor layers which are disposed shallower than the depth of the well region in the well region except for a lower portion of the gate electrode film.

Claims

1. A semiconductor device comprising:

a well region having a first conductivity type of a high resistance disposed in a given depth from a surface of a semiconductor substrate;

a plurality of trenches extending from the surface of the well region to a middle of the given depth;

a gate insulating film disposed on a surface of a convex/concave portion made by the plurality of trenches;

a gate electrode embedded into the plurality of trenches;

a gate electrode film disposed on the surface of the semiconductor substrate in contact with the gate electrode embedded into the plurality of trenches in the convexo-concave portion except for a portion in a vicinity of both ends of the plurality of trenches; and

a source region and a drain region each having a second conductivity of a low resistance disposed shallower than the depth of the well region in the well region except for a lower portion of the gate electrode film.

2. A semiconductor device according to claim 1, further comprising a DDD structure.

3. A semiconductor device according to claim 1, further comprising an LDMOS structure.

4. A semiconductor device according to claim 1, wherein a width of a convex portion in the convex/concave portion is approximately 1,000 Å

.

5. A semiconductor device according to claim 1, wherein an inner portion of the convex portion in the convex/concave portion has such a width as to turn into a full depletion when the semiconductor device is in an ON state.

6. A semiconductor device according to claim 1, wherein the semiconductor device is combined with a twin well technique.

7. A semiconductor device according to claim 1, wherein a conductivity type is inverted.

8. A method of manufacturing the semiconductor device according to claim 1 comprising the steps of:

forming the trench regions; and

forming the well region by oblique ion implantation in multiple directions.

9. A method of manufacturing the semiconductor device according to claim 1 having a step of forming the well region, the step of forming the well region comprising the steps of:

forming a first conductivity type in a first semiconductor region through ion implantation on the surface of the semiconductor substrate;

forming a semiconductor on the surface of the semiconductor substrate through epitaxial growth; and

forming a second conductivity type semiconductor region, having the same conductivity type as the first semiconductor region, through ion implantation on a surface of the semiconductor formed through epitaxial growth.