Trench MOSFET with sidewall spacer gates

• US 20060223260A1
• Filed: 04/03/2006
• Published: 10/05/2006
• Est. Priority Date: 04/05/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Henson, Timothy D.
• Granted Patent: US 7,671,441 B2
• Time in Patent Office: Days
• US Class Current: 438/243
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor power device includes a semiconductor body with a plurality of gate trenches formed therein. Disposed within each gate trench is a spacer gate that extends along at least a portion of the sidewalls of the gate trench but not along at least a portion of the bottom surface of the trench. The spacer gate of each gate trench may also include a layer of silicide along outer surfaces thereof. The semiconductor body may include a channel region and each gate trench may extend through the channel region and into the semiconductor body. Formed at the bottom of each gate trench within the semiconductor body may be a tip implant of the same conductivity as the semiconductor body. In addition, a deep body implant of the same conductivity as the channel region may be formed at the base of the channel region.

Claims

1. A power semiconductor device, comprising:

a semiconductor body of a first conductivity type;

a plurality of trenches along a surface of said semiconductor body, each trench having sidewalls and a bottom surface;

a gate insulation layer lining at least portions of the sidewalls and the bottom surface of each of said trenches; and

a gate electrode disposed within each of said trenches, said gate electrode within each trench extending along at least a portion of the sidewalls of said trench but not along at least a portion of the bottom surface of said trench.

2. The power semiconductor device of claim 1, further comprising an insulation body disposed within each of said trenches and covering outer surfaces of said gate electrode disposed within each trench.

3. The power semiconductor device of claim 2, wherein said insulation body within each trench extends from the bottom surface of said trench towards an upper end of said trench.

4. The power semiconductor device of claim 1, wherein each of said gate electrodes includes a silicide layer along outer surfaces thereof.

5. The power semiconductor device of claim 4, wherein said silicide layer of each gate electrode within each trench extends from the bottom surface of said trench towards an upper end of said trench.

6. The power semiconductor device of claim 1, wherein said gate insulation layer within each trench has a substantially uniform thickness along the sidewalls and the bottom surface of said trench.

7. The power semiconductor device of claim 1, wherein said gate electrode within each trench has a thickness of about 100 Å

to about 1000 Å

along the sidewalls of said trench.

8. The power semiconductor device of claim 1, further comprising:

a channel region of a second conductivity type in said semiconductor body, wherein each of said trenches extends into said channel region; and

a tip implant of said first conductivity type formed within said semiconductor body at the bottom of each trench.

9. The power semiconductor device of claim 8, further comprising a deep body implant of said second conductivity type formed along a bottom of said channel region.

10. The power semiconductor device of claim 8, wherein said tip implant at the bottom of each trench is aligned to said gate electrode within said trench.

11. A power semiconductor device, comprising:

a semiconductor body of a first conductivity type;

a plurality of trenches along a surface of said semiconductor body, each trench having sidewalls and a bottom surface;

a gate insulation layer lining at least portions of the sidewalls and the bottom surface of each of said trenches; and

spacer gates disposed along at least a portion of the sidewalls of each of said trenches, said spacer gates within each trench forming a void therein that extends from an upper end of said trench to the bottom surface of said trench.

12. The power semiconductor device of claim 11, further comprising an insulation body disposed within said void formed by each of said spacer gates and covering outer surfaces of said spacer gates.

13. The power semiconductor device of claim 11, wherein each of said spacer gates includes a silicide layer along outer surfaces thereof.

14. The power semiconductor device of claim 11, further comprising:

a channel region of a second conductivity type in said semiconductor body, wherein each of said trenches extends into said channel region; and

a tip implant of said first conductivity type formed within said semiconductor body at the bottom of each trench.

15. The power semiconductor device of claim 14, further comprising a deep body implant of said second conductivity type formed along a bottom of said channel region.

16. A method for fabricating a power semiconductor device, comprising the steps of:

etching a plurality of trenches in a semiconductor body comprising an epitaxial layer of a first conductivity type and a channel region of a second conductivity type formed atop said epitaxial layer, each trench having sidewalls and a bottom surface;

forming a gate insulation layer along at least portions of the sidewalls and the bottom surface of each of said trenches;

forming a layer of doped polysilicon within each of said trenches;

etching said doped polysilicon within each trench to expose at least a portion of the bottom surface of each trench and thereby forming a gate electrode within each trench, said gate electrode within each trench extending along at least a portion of the sidewalls of said trench.

17. The method of claim 16, further comprising the step of forming an insulation body within each of said trenches such that said insulation body covers outer surfaces of said gate electrode disposed within each trench.

18. The method of claim 16, further comprising the step of forming a silicide layer along outer surfaces of each of said gate electrodes.

19. The method of claim 16, wherein each of said plurality of trenches extends into said channel region, said method further comprising the step of forming a tip implant of said first conductivity type at the bottom of each trench and that extends into said epitaxial layer.

20. The method of claim 19, wherein each of said gate electrodes is used as mask to form said tip implant at the bottom of each trench.

21. The method of claim 19, further comprising the step of forming a deep body implant of said second conductivity type along a bottom of said channel region.