Method of forming transistor using step STI profile in memory device

• US 20060223263A1
• Filed: 12/29/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hu, Hyun
• Granted Patent: US 7,659,179 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A method of forming a memory device includes forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and etching a portion of the semiconductor substrate provided within the active region to define a step profile, so that the active region includes a first vertical portion and an upper primary surface, the first vertical portion extending above the upper primary surface.

Claims

1. A method of forming a memory device, comprising:

forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and

etching a portion of the semiconductor substrate provided within the active region to define a step profile, so that the active region includes a first vertical portion and an upper primary surface, the first vertical portion extending above the upper primary surface.

2. The method of claim 1, further comprising:

forming a first spacer provided adjacent to the first isolation structure.

3. The method of claim 2, wherein the first spacer is provided with a slope and lies over the first vertical portion.

4. The method of claim 2, wherein the etching step provides a second vertical portion that extends above the upper primary surface of the active region, the method further comprising:

forming a second spacer provided adjacent the second isolation,

wherein the first and second isolation structures are first and second shallow trench isolation structures,

wherein the first and second spacers are used as a mask to etch the substrate.

5. The method of claim 1, at least a first portion of the active region is provided with dopants by performing a slanted implantation method.

6. The method of claim 5, wherein the slanted implantation method involves implanting the dopants into the first portion of the active region using an implantation angle of 4-15 degrees.

7. The method of claim 6, wherein at least a second portion of the active region is provided with dopants by performing a vertical implantation method, wherein the vertical implantation method involves implanting the dopants into the second portion of the active region using an implantation angle of substantially 0 degree.

8. The method of claim 2, wherein the first spacer is provided with a width of 100 Å

to 1000 Å

.

9. The method of claim 2, wherein the first spacer is formed using one of an oxide film or a nitride film.

10. The method of claim 1, further comprising:

annealing the semiconductor substrate after the etching step to round a corner defined by the step profile.

11. The method of claim 10, wherein the annealing is performed at a temperature between 800°

and 1100°

.

12. The method of claim 11, wherein a dielectric film having a thickness of 10 Å

to 30 Å

is formed using the annealing step.

13. The method of claim 10, further comprising:

removing an oxide film formed over the substrate as a result of the annealing; and

thereafter, forming a tunnel oxide over the semiconductor substrate within the active region.

14. The method of claim 13, wherein the tunnel oxide is formed using a radical oxidization process.

15. A method of forming a memory device, comprising:

forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween;

forming first and second spacers provided adjacent to the first and second isolation structures, respectively, the first and second spacers exposing a portion of the substrate; and

etching the exposed portion of the substrate to define a step profile, so that the active region includes first and second vertical portions and an upper primary surface, the first and second vertical portions extending above the upper primary surface, the first vertical portion being provided directly below the first spacer, the second vertical portion being provided directly below the second spacer.