Formation of deep via airgaps for three dimensional wafer to wafer interconnect

• US 20060223301A1
• Filed: 12/16/2005
• Published: 10/05/2006
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Kunnen, Eddy, Carbonell, Laure Elisa, Vanhaelemeersch, Serge
• Granted Patent: US 7,338,896 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

Claims

1. A method for fabricating a vertical stack of at least two wafers to create a three dimensional stacked semiconductor device using a through wafer via, the method comprising the steps of:

patterning at least one via having sidewalls in a first wafer;

forming a partially filled-in portion of the via, wherein the partially filled-in portion comprises a sacrificial material, whereby a portion of the sidewalls is exposed and a portion of the sidewalls is covered by the sacrificial material;

forming spacers on the exposed portion of the sidewalls, whereby an opening to the via is narrowed;

removing the sacrificial material through the narrowed opening;

sealing the opening by depositing a sealing layer above the spacers, whereby an airgap with an airgap plug is formed;

creating at least one contact hole in the airgap plug;

filling the contact hole with a conductive material such that at least one contact plug is created;

depositing a conductive structure onto the contact plug;

making a contact to the contact plug by performing a conventional back end of line processing step;

thinning a backside of the first wafer such that the airgap is opened, thereby forming a through wafer via or a deep via;

depositing a conductive material in the through wafer via or the deep via to create in the first wafer either a through wafer via filled with conductive material or a deep via filled with conductive material, respectively; and

contacting the backside of the first wafer through the through wafer via filled with conductive material or through the deep via filled with conductive material to an interconnect structure situated in a frontside of the second wafer.

2. The method of claim 1, wherein the step of forming the partially filled-in portion of the via comprises the steps of:

completely filling the via with a sacrificial material; and

etching back a portion of the sacrificial material, whereby a portion of the sidewalls is exposed and a portion of the sidewalls is covered by the sacrificial material.

3. The method according to claim 1, further comprising the step of:

forming a separating layer in the via,. the separating layer comprising a thermally grown silicon-dioxide layer.

5. The method according to claim 1, wherein the step of forming the spacers comprises the steps of:

depositing a nitride layer as a dry etch endpoint triggering layer;

thereafter

closing or narrowing the opening by depositing a conformal layer comprising a spacer material within the via; and

anisotropically etching back the spacer material, whereby spacers are formed.

6. The method according to claim 1, wherein the sacrificial material is removed by an isotropic etching process.

7. The method according to claim 1, wherein sealing the opening by depositing a sealing layer above the spacers comprises depositing a sealing layer by a conformal deposition process.

8. The method according to claim 7, wherein the conformal deposition process is a chemical vapor deposition process.

9. The method according to claim 1, further comprising a step of:

planarizing the sealing layer.

10. The method according to claim 9, wherein the planarizing step comprises a chemical mechanical planarizing step.

11. The method according to claim 1, wherein the first wafer is a silicon wafer.

12. The method according to claim 1, wherein the sacrificial material is poly-silicon.

13. The method according to claim 1, wherein the spacer material is silicon dioxide.

14. The method according to claim 1, wherein the via has a diameter of from about 1 μ

m to about 10 μ

m.

15. The method according to claim 1, wherein the via has a diameter of from about 2 μ

m to about 6 μ

m.

16. The method according to claim 1, wherein the via has a depth in the first wafer of from about 10 μ

m to about 100 μ

m.

17. The method according to claim 1, wherein the via has a depth in the first wafer of from about 20 μ

m to about 50 μ

m.

18. The method of claim 1, wherein the contact hole is created during front end of line processing by dry etching.

19. The method of claim 1, wherein at least one contact plug in the airgap via is created simultaneously with at least one contact plug in an active device of the semiconductor device.

20. The method of claim 1, wherein at least one contact hole has a diameter of from about 100 nm to about 200 nm.

21. The method of claim 1, further comprising the step of:

depositing an etch stop layer and thereafter depositing a dielectric layer on top of the etch stop layer, wherein the depositing steps are conducted after the creation of the airgap with the airgap plug.

22. The method of claim 21, wherein the etch stop layer is selected from the group consisting of a SiON layer, a Si₃N₄ layer, a SiC layer, and a SiCN layer.

23. The method of claim 1, further comprising the step of:

depositing a barrier layer onto the sidewalls of the contact hole.

24. The method of claim 1, further comprising the step of:

depositing a conformal barrier layer into the contact hole prior to filling the contact hole with a conductive material, wherein the conductive material comprises tungsten.

25. The method of claim 23, wherein the barrier layer comprises a material selected from the group consisting of ruthenium, Ta(N), Ti(N), TaSiN, TiSiN, TiW, and W(C)N.

26. The method of claim 1, wherein thinning the backside of the wafer comprises at least one chemical removal process or mechanical removal process.

27. The method of claim 1, further comprising the steps of:

depositing a barrier layer; and

thereafter

depositing a seed layer or catalyst nuclei onto sidewalls of the through wafer via or the deep via, wherein the depositing steps are conducted after the step of thinning the backside of the wafer.

28. The method of claim 1, wherein the conductive material used to fill the through wafer via or the deep via is copper.

29. The method of claim 1, wherein the step of depositing a conductive material in the through wafer via or the deep via uses a method selected from the group consisting of physical vapor deposition, chemical vapor deposition, electroless deposition, and direct plating.

30. A semiconductor device obtainable by a method according to claim 1.

4. The method according to claim I, further comprising the step of:

depositing at least one additional isolation layer within the via, wherein the isolation layer comprises a silicon-dioxide layer on top of either a silicon-nitride layer, a Cu barrier layer, or a ruthenium barrier layer.

31. A three dimensional stacked semiconductor device, the device comprising:

a first wafer comprising at least one active integrated circuit device and having at least one through wafer via filled with a conductive material, the through wafer via having a top, a bottom, and sidewalls situated in a wafer substrate;

a second wafer comprising at least one active integrated circuit device;

the active devices of the first wafer and the second wafer making contact with each other through the through wafer via.

32. The three dimensional stacked semiconductor device of claim 31, wherein the conductive material in the through wafer via comprises at least one material selected from the group consisting of a metal, a conductive polymer, a metal silicide, conductive carbon nanotubes, and conductive nanowires.

33. The three dimensional stacked semiconductor device of claim 31, wherein the conductive material in the through wafer via comprises at least one metal selected from the group consisting of copper, aluminum, and tungsten.

34. The three dimensional stacked semiconductor device of claim 31, wherein the sidewalls of the through wafer via comprise at least one isolation layer.

35. The three dimensional stacked semiconductor device of claim 31, wherein the sidewalls of the through wafer via comprise at least one isolation layer, wherein the isolation layer comprises a silicon dioxide layer on top of a silicon-nitride barrier layer, a copper barrier layer, or a ruthenium barrier layer.

36. The three dimensional stacked semiconductor device of claim 31, wherein the sidewalls of the through wafer via comprise at least one isolation layer, wherein the isolation layer comprises a silicon-dioxide layer on top of a copper barrier layer, the barrier layer comprising at least one material selected from the group consisting of Ru, Ta(N), Ti(N), TaSiN, TiSiN, TiW, and W(C)N.

37. The three dimensional stacked semiconductor device of claim 31, wherein the sidewalls of the through wafer via further comprise a seedlayer or catalysts on top of at least one isolation layer.

38. The three dimensional stacked semiconductor device of claim 31, wherein the top of the through wafer via comprises at least one contact plug.

39. The three dimensional stacked semiconductor device of claim 31, wherein at least one contact plug is partly situated in the conductive material of the through wafer via.

40. The three dimensional stacked semiconductor device of claim 31, wherein the contact plug comprises tungsten.