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Self-aligned contacts for transistors

  • US 20060223302A1
  • Filed: 03/31/2005
  • Published: 10/05/2006
  • Est. Priority Date: 03/31/2005
  • Status: Active Grant
First Claim
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1. A method comprising:

  • patterning an etch-resistant material to create an opening that resides above a transistor gate structure and above areas adjacent to the transistor gate structure;

    performing a selective etch through the opening that does not etch the transistor gate structure but does etch material that resides laterally with respect to the transistor gate structure in order to expose tops, immediately adjacent to the transistor gate structure, of drain and source regions of a diffusion layer of the transistor;

    depositing conductive material that covers respective tops of the drain and source regions of the diffusion layer of the transistor to a depth that does not short the drain and source regions of the diffusion layer of the transistor;

    forming a layer above the conductive material;

    forming, through the layer above the conductive material, contacts to respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer of the transistor.

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