Self-aligned contacts for transistors

• US 20060223302A1
• Filed: 03/31/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Daedalus Prime LLC (Daedalus Group LLC)
• Original Assignee: Intel Corporation
• Inventors: Doyle, Brian S., Chang, Peter L.D.
• Granted Patent: US 7,563,701 B2
• Time in Patent Office: Days
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

Self-aligned contacts for transistors and methods for fabricating the contacts are described. An etch resistant material is patterned to create an opening that resides above a transistor gate structure. A selective etch is performed through the opening that does not etch the transistor gate structure but does etch material that resides laterally with respect to the transistor gate structure in order to expose tops, immediately adjacent to the transistor gate structure, of drain and source regions of a diffusion layer of the transistor. Conductive material is deposited that covers respective tops of the drain and source regions of the diffusion layer of the transistor to a depth that does not short the drain and source region of the diffusion layer of the transistor. A layer above the conductive material is formed. Contacts are formed through the layer above the conductive material to respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer of the transistor.

Claims

1. A method comprising:

patterning an etch-resistant material to create an opening that resides above a transistor gate structure and above areas adjacent to the transistor gate structure;

performing a selective etch through the opening that does not etch the transistor gate structure but does etch material that resides laterally with respect to the transistor gate structure in order to expose tops, immediately adjacent to the transistor gate structure, of drain and source regions of a diffusion layer of the transistor;

depositing conductive material that covers respective tops of the drain and source regions of the diffusion layer of the transistor to a depth that does not short the drain and source regions of the diffusion layer of the transistor;

forming a layer above the conductive material;

forming, through the layer above the conductive material, contacts to respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer of the transistor.

2. The method of claim 1, wherein the transistor gate structure comprises a transistor gate and spacers adjacent to the transistor gate.

3. The method of claim 1, wherein the transistor gate structure comprises a plurality of spaced transistor gates with respective adjacent spacers.

4. The method of claim 2, further comprising forming, through the layer above the conductive material, a contact to the gate of the transistor.

5. The method of claim 1, further comprising forming metal lines that contact respective tops of the contacts.

6. The method of claim 1, wherein the transistor is a trigate transistor.

7. The method of claim 2, wherein the transistor gate is comprised of metal and the spacers are comprised of silicon nitride.

8. The method of claim 1, wherein depositing conductive material comprises:

depositing contact metal;

polishing the contact metal until the contact metal is planarized with respect to a top of transistor gate structure.

9. The method of claim 1, wherein forming contacts to respective portions of the conductive material comprises:

patterning photoresist on the layer above the conductive material;

etching (1) a first via through the layer above the conductive material to a portion of the conductive material that covers the top of the drain region of the diffusion layer of the transistor and (2) a second via through the layer above the conductive material to a portion of the conductive material to a portion of the conductive material that covers the top of the source region of the diffusion layer of the transistor;

depositing contact metal within the first and second vias.

10. A method comprising:

polishing a wafer that includes a gate, spacers adjacent to the gate, and a diffusion layer with drain and source regions, wherein the polishing stops at a top of the spacers;

removing an upper portion of the gate so that a top of the gate is recessed with respect to the top of the spacers such that a gate recess is formed;

filling the gate with a protective material;

patterning an etch-resistant material to create an opening that resides (1) above the spacers, (2) above the protective material, and (3) above areas adjacent to the spacers;

performing a selective etch through the opening that does not etch the gate, the protective material, or the spacers, but does etch material that resides laterally with respect to the spacers in order to expose tops, immediately adjacent to the spacers, of the drain and source regions of the diffusion layer;

depositing conductive material that covers respective tops of the drain and source regions of the diffusion layer to a depth that does not short the drain and source regions of the diffusion layer;

forming a layer above the conductive material;

forming, in the layer above the conductive material, metal lines that contact respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer.

11. The method of claim 10, wherein the protective material is silicon nitride.

12. The method of claim 10, further comprising forming a contact to the gate of the transistor.

13. The method of claim 12, wherein forming a contact to the gate of transistor comprises:

prior to performing a selective etch, removing the protective material from the gate recess and removing partial upper portions of the spacers in order to form a spacer recess;

depositing contact material in the spacer recess;

forming, in the layer above the conductive material, a metal line that contacts the conductive material in the spacer recess.

14. The method of claim 12, wherein forming a contact to the gate of the transistor comprises:

forming an opening in the layer above the conductive material that exposes a top of the spacers and the protective material filling the gate recess;

removing the protective material from the gate recess and removing partial upper portions of the spacers in order to form a spacer recess;

depositing contact material in the spacer recess;

filling the opening in the layer above the conductive material with a metal line that contacts the contact material in the spacer recess.

15. The method of claim 10, wherein the transistor is a trigate transistor.

16. The method of claim 10, wherein the transistor gate is comprised of metal and the spacers are comprised of silicon nitride.

17. The method of claim 10, wherein depositing conductive material comprises:

depositing contact metal;

polishing the contact metal until the contact metal is planarized with respect to a top of the spacers.

18. The method of claim 10, wherein forming metal lines comprises:

patterning photoresist on the layer above the conductive material;

etching a first opening in the layer above conductive material that exposes a top of the conductive material that covers the top of the drain region of the diffusion layer of the transistor;

etching a second opening in the layer above the conductive material that exposes a top of the conductive material that covers the top of the source region of the diffusion layer of the transistor;

depositing metal lines within the first and second openings.

19. An apparatus comprising:

a gate of a transistor;

a first spacer adjacent to a first side of the gate;

a second spacer adjacent to a second side of the gate;

a diffusion layer of the transistor, wherein the diffusion layer includes a source region and a drain region;

a first conductive region adjacent to the first spacer, wherein the first conductive region is superadjacent to and contacts the source region of the diffusion layer of the transistor, wherein the first conductive region is planarized with respect to a top of the first spacer;

a second conductive region adjacent to the second spacer, wherein the second conductive region is superadjacent to and contacts the drain region of the diffusion layer of the transistor, wherein the second conductive region is planarized with respect to a top of the second spacer;

a first contact residing in a first via above the first conductive region and contacting the first conductive region;

a second contact residing in a second via above the second conductive region and contacting the second conductive region.

20. The apparatus of claim 19, further comprising a third contact residing in a third via above the gate and contacting the gate.

21. The apparatus of claim 19, further comprising:

a first metal line residing superadjacent to the first contact and contacting the first contact;

a second metal line residing superadjacent to the second contact and contacting the second contact.

22. The apparatus of claim 19, wherein the transistor is a trigate transistor.

23. The apparatus of claim 19, wherein the gate of the transistor is comprised of metal and wherein each of the first and second spacers is comprised of silicon nitride.

24. The apparatus of claim 19, wherein a protective material resides between the first and second spacers and superadjacent to the gate.

25. The apparatus of claim 24, wherein the protective material is silicon nitride.