System for parallel updating flash memory and method for the same
First Claim
1. A parallel memory updating method, applied for a host computer, the host computer being capable of updating non-volatile memories of multiple peripheral devices via an interface at the same time, the method comprising:
- (a) separating one non-volatile memory updating flow into one or more sub-flows for different peripheral devices of the host computer, wherein each sub-flow has a specific period of execution time; and
(b) executing the sub-flows individually.
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Abstract
A parallel memory updating method and its system are proposed in the present invention. The present invention is applied for a host computer and makes the host computer capable of using pipeline concept to update multiple peripheral devices at the same time. Thus, the updating efficiency is greatly improved. The parallel flash memory updating method includes the following steps: sending a START_FLASH_CMD command via an IDE interface to make the peripheral devices switch to a flash memory updating mode; send out a WRITE_ENABLE command to enable a writing function of the flash memories of the peripheral devices; and writing firmware data to the flash memories of the peripheral devices.
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Citations
10 Claims
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1. A parallel memory updating method, applied for a host computer, the host computer being capable of updating non-volatile memories of multiple peripheral devices via an interface at the same time, the method comprising:
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(a) separating one non-volatile memory updating flow into one or more sub-flows for different peripheral devices of the host computer, wherein each sub-flow has a specific period of execution time; and
(b) executing the sub-flows individually. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A parallel flash memory updating system, comprising:
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(a) an interface electrically connected to a host computer and multiple peripheral devices, wherein the host computer having a parallel memory updating program and each of the peripheral devices having a non-volatile memory; and
(b) a non-volatile memory controller, wherein the parallel memory updating program uses the interface to drive the non-volatile memory controller and a pipeline architecture to update the non-volatile memories of the peripheral devices. - View Dependent Claims (10)
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Specification