Sequencer address management
First Claim
1. A method, comprising:
- receiving a logical sequencer address specified in a user instruction;
assigning the logical sequencer address to one of a plurality of physical sequencer frames;
receiving the logical sequencer address in association with a second user instruction; and
providing an identifier to indicate the assigned physical sequencer frame.
1 Assignment
0 Petitions
Accused Products
Abstract
Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.
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Citations
21 Claims
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1. A method, comprising:
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receiving a logical sequencer address specified in a user instruction;
assigning the logical sequencer address to one of a plurality of physical sequencer frames;
receiving the logical sequencer address in association with a second user instruction; and
providing an identifier to indicate the assigned physical sequencer frame. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A mapping manager for a multi-sequencer multithreading system, comprising:
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rationing logic to assign a logical sequencer address to a physical sequencer; and
translation logic to receive the logical sequencer address and to provide an identifier associated with an assigned physical sequencer;
- View Dependent Claims (12, 13, 14, 15, 16)
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17. A multi-sequencer multithreading system comprising:
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a memory system to store a user program;
a plurality of physical sequencers capable of concurrent thread execution; and
a mapping manager to map an address for a logical sequencer to a physical sequencer frame. - View Dependent Claims (18, 19, 20, 21)
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Specification