Sequencer address management

• US 20060224858A1
• Filed: 04/05/2005
• Published: 10/05/2006
• Est. Priority Date: 04/05/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zou, Xiang, Shen, John, Bigbee, Bryant, Wang, Hong, Sethi, Prashant, Chinya, Gautham N., Rodgers, Scott Dion, Brandt, Jason W., Kaushik, Shivnandan D., Hammarlund, Per, Patel, Baiju V., Hankins, Richard A., Reid, John L., Rakvic, Ryan N., Shah, Sanjiv M., Abel, James Charles, Held, James Paul, Poulsen, David K., Carmean, Douglas M.
• Granted Patent: US 7,743,233 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Claims

1. A method, comprising:

receiving a logical sequencer address specified in a user instruction;

assigning the logical sequencer address to one of a plurality of physical sequencer frames;

receiving the logical sequencer address in association with a second user instruction; and

providing an identifier to indicate the assigned physical sequencer frame.

2. The method of claim 1, further comprising:

recording a mapping of the logical sequencer address and the identifier of the assigned physical sequencer frame in a mapping structure.

3. The method of claim 2, wherein:

said providing further comprises consulting the mapping structure to determine the assigned physical sequencer frame.

4. The method of claim 2, wherein:

the mapping structure resides in a memory storage.

5. The method of claim 4, further comprising:

buffering at least part of the mapping structure in a hardware buffer.

6. The method of claim 5, wherein:

said providing further comprises consulting the hardware buffer to determine the assigned physical sequencer frame.

7. The method of claim 1, wherein:

said physical sequencer frame includes only a single physical sequencer.

8. The method of claim 1, wherein:

said assigning further comprises determining if at least one of the plurality of physical sequencer frames is currently not assigned.

9. The method of claim 1, wherein:

said assigning further comprises selecting a victim from among a plurality of active sequencers.

10. The method of claim 1, wherein:

said assigning further comprises assessing one or more attributes of the plurality physical of sequencer frames.

11. A mapping manager for a multi-sequencer multithreading system, comprising:

rationing logic to assign a logical sequencer address to a physical sequencer; and

translation logic to receive the logical sequencer address and to provide an identifier associated with an assigned physical sequencer;

12. The mapping manager of claim 11, wherein:

said rationing logic further comprises sharing logic to allow the first sequencer to access the second sequencer under certain predetermined conditions.

13. The mapping manager of claim 11, further comprising:

relocation logic to swap context information for a sequencer to a backing store.

14. The mapping manager of claim 11, further comprising:

protection logic to prevent a first sequencer from accessing a second sequencer without permission.

15. The mapping manager of claim 11, wherein:

said translation logic is further to receive said logical sequencer address responsive to a reference in a user instruction.

16. The mapping manager of claim 11, further comprising:

scheduling logic to schedule a set of logical sequencers for execution on a smaller set of physical sequencers.

17. A multi-sequencer multithreading system comprising:

a memory system to store a user program;

a plurality of physical sequencers capable of concurrent thread execution; and

a mapping manager to map an address for a logical sequencer to a physical sequencer frame.

18. The system of claim 17, wherein:

said actual sequencer frame includes only one sequencer.

19. The system of claim 17, wherein:

said mapping manager is further to provide an identifier associated with the physical sequencer frame responsive to receiving the logical sequencer address.

20. The system of claim 17, further comprising:

a backing store to store context information associated with the logical sequencer.

21. The system of claim 17, further comprising:

a logical sequencer context queue to store context information for the logical sequencer.