System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave

• US 20060224935A1
• Filed: 12/01/2005
• Published: 10/05/2006
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Granted Patent: US 7,447,981 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/2966 Turbo codes concatenated with another code, e.g. an outer block code

Abstract

System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed at either end of a communication channel (e.g., at a transmitter end when performing encoding and/or at a receiver end when performing decoding). By combining different coding types within a communication system, the error correcting capabilities of the overall system is significantly improved. The appropriate combination of turbo code and/or LDPC code along with RS code allows for error correction or various error types including random error and burst error (or impulse noise).

Claims

1. An apparatus, comprising:

a RS (Reed-Solomon) encoder that is operable to encode a first bit stream thereby generating a RS coded bit stream;

a first interleaver that is operable to interleave the-RS coded bit stream thereby generating an m-bit symbol sequence;

an encoder that is operable to encode a second bit stream, using an LDPC (Low Density Parity Check) code or a turbo code, thereby generating an LDPC or turbo coded bit stream;

a second interleaver that is operable to interleave the LDPC or turbo coded bit stream thereby generating an n-bit symbol sequence; and

a symbol mapper that is operable to;

receive the m-bit symbol sequence;

receive the n-bit symbol sequence;

combine selected m-bit symbols from the m-bit symbol sequence and selected n-bit symbols from the n-bit symbol sequence thereby generating an m+n bit symbol sequence; and

symbol map the m+n bit symbol sequence according to a constellation having 2^(m+n) constellation points and a corresponding mapping of the 2^(m+n) constellation points thereby generating a sequence of discrete valued modulation symbols.

2. The apparatus of claim 1, further comprising:

a convolutional interleaver that is operable to interleave the sequence of discrete valued modulation symbols thereby generating a scrambled sequence of discrete valued modulation symbols; and

a modulator that is operable to;

transform the scrambled sequence of discrete valued modulation symbols into a continuous time transmit signal that comports with a communication channel; and

launch the continuous time transmit signal into the communication channel.

3. The apparatus of claim 2, wherein:

the RS encoder is operable to introduce redundancy within the RS coded bit stream to enable error correction of burst error that may be incurred by the continuous time transmit signal within the communication channel.

4. The apparatus of claim 2, wherein:

the encoder is operable to introduce redundancy within the LDPC or turbo coded bit stream to enable error correction of random errors that may be incurred by the continuous time transmit signal within the communication channel.

5. The apparatus of claim 1, further comprising:

a separator that is operable to;

receive an input bit stream; and

partition the input bit stream into the first bit stream that is provided to the RS encoder and the second bit stream that is provided to the encoder that employs the LDPC or turbo code.

6. The apparatus of claim 5, wherein:

the separator is operable to select bits from the input bit stream such that;

a first bit of the input bit stream is provided to the first bit stream;

a second bit of the input bit stream is provided to the second bit stream;

a third bit of the input bit stream is provided to the first bit stream; and

a fourth bit of the input bit stream is provided to the second bit stream.

7. The apparatus of claim 5, wherein:

the separator is operable to select bits from the input bit stream such that;

a first plurality of bits of the input bit stream is provided to the first bit stream;

a second plurality of bits of the input bit stream is provided to the second bit stream;

a third plurality of bits of the input bit stream is provided to the first bit stream; and

a fourth plurality of bits of the input bit stream is provided to the second bit stream.

8. An apparatus, comprising:

a RS (Reed-Solomon) encoder that is operable to encode an input bit stream thereby generating a RS coded bit stream;

a separator that is operable to partition the RS coded bit stream into a first RS coded bit stream and a second RS coded bit stream;

a first interleaver that is operable to interleave the first RS coded bit stream thereby generating an m-bit symbol sequence;

a convolutional interleaver that is operable to interleave the second RS coded bit stream thereby generating a scrambled second RS coded bit stream;

an encoder that is operable to encode the scrambled second RS coded bit stream, using an LDPC (Low Density Parity Check) code or a turbo code, thereby generating an LDPC or turbo coded bit stream;

a second interleaver that is operable to interleave the LDPC or turbo coded bit stream thereby generating an n-bit symbol sequence; and

a symbol mapper that is operable to;

receive the m-bit symbol sequence;

receive the n-bit symbol sequence;

combine selected m-bit symbols from the m-bit symbol sequence and selected n-bit symbols from the n-bit symbol sequence thereby generating an m+n bit symbol sequence; and

symbol map the m+n bit symbol sequence according to a constellation having 2^(m+n) constellation points and a corresponding mapping of the 2^(m+n) constellation points thereby generating a sequence of discrete valued modulation symbols.

9. The apparatus of claim 8, further comprising:

at least one additional convolutional interleaver that is operable to interleave the sequence of discrete valued modulation symbols thereby generating a scrambled sequence of discrete valued modulation symbols;

a modulator that is operable to;

transform the scrambled sequence of discrete valued modulation symbols into a continuous time transmit signal that comports with a communication channel; and

launch the continuous time transmit signal into the communication channel.

10. The apparatus of claim 9, wherein:

the RS encoder is operable to introduce redundancy within the RS coded bit stream to enable error correction of burst error that may be incurred by the continuous time transmit signal within the communication channel.

11. The apparatus of claim 9, wherein:

the encoder is operable to introduce redundancy within the LDPC or turbo coded bit stream to enable error correction of random errors that may be incurred by the continuous time transmit signal within the communication channel.

12. The apparatus of claim 8, wherein:

the separator is operable to select bits from the RS coded bit stream such that;

a first bit of the RS coded bit stream is provided to the first RS coded bit stream;

a second bit of the RS coded bit stream is provided to the second RS coded bit stream;

a third bit of the RS coded bit stream is provided to the first RS coded bit stream; and

a fourth bit of the RS coded bit stream is provided to the second RS coded bit stream.

13. The apparatus of claim 8, wherein:

the separator is operable to select bits from the RS coded bit stream such that;

a first plurality of bits of the RS coded bit stream is provided to the first RS coded bit stream;

a second plurality of bits of the RS coded bit stream is provided to the second RS coded bit stream;

a third plurality of bits of the RS coded bit stream is provided to the first RS coded bit stream; and

a fourth plurality of bits of the RS coded bit stream is provided to the second RS coded bit stream.

14. A method, comprising:

encoding a first bit stream using a RS (Reed-Solomon) code thereby generating a RS coded bit stream;

interleaving the RS coded bit stream using a first interleave thereby generating an m-bit symbol sequence;

encoding a second bit stream using an LDPC (Low Density Parity Check) code or a turbo code thereby generating an LDPC or turbo coded bit stream;

interleaving the LDPC or turbo coded bit stream using a second interleave thereby generating an n-bit symbol sequence;

combining selected m-bit symbols from the m-bit symbol sequence and selected n-bit symbols from the n-bit symbol sequence thereby generating an m+n bit symbol sequence;

symbol mapping the m+n bit symbol sequence according to a constellation having 2^(m+n) constellation points and a corresponding mapping of the 2^(m+n) constellation points thereby generating a sequence of discrete valued modulation symbols;

convolutional interleaving the sequence of discrete valued modulation symbols thereby generating a scrambled sequence of discrete valued modulation symbols;

transforming the scrambled sequence of discrete valued modulation symbols into a continuous time transmit signal that comports with a communication channel; and

launching the continuous time transmit signal into the communication channel.

15. The method of claim 14, further comprising:

receiving an input bit stream; and

partitioning the input bit stream into the first bit stream that is provided to the RS encoder and the second bit stream that is provided to the encoder that employs the LDPC or turbo code.

16. The method of claim 15, wherein:

a first bit of the input bit stream is provided to the first bit stream;

a second bit of the input bit stream is provided to the second bit stream;

a third bit of the input bit stream is provided to the first bit stream; and

a fourth bit of the input bit stream is provided to the second bit stream.

17. The method of claim 15, wherein:

a first plurality of bits of the input bit stream is provided to the first bit stream;

a second plurality of bits of the input bit stream is provided to the second bit stream;

a third plurality of bits of the input bit stream is provided to the first bit stream; and

a fourth plurality of bits of the input bit stream is provided to the second bit stream.

18. A method, comprising:

encoding an input bit stream using a RS (Reed-Solomon) code thereby generating a RS coded bit stream;

separating the RS coded bit stream into a first RS coded bit stream and a second RS coded bit stream;

interleaving the first RS coded bit stream using a first interleave thereby generating an m-bit symbol sequence;

convolutional interleaving the second RS coded bit stream using a first convolutional interleave thereby generating a scrambled second RS coded bit stream;

encoding the scrambled second RS coded bit stream, using an LDPC (Low Density Parity Check) code or a turbo code, thereby generating an LDPC or turbo coded bit stream;

interleaving the LDPC or turbo coded bit stream using a second interleave thereby generating an n-bit symbol sequence; and

combining selected m-bit symbols from the m-bit symbol sequence and selected n-bit symbols from the n-bit symbol sequence thereby generating an m+n bit symbol sequence;

symbol mapping the m+n bit symbol sequence according to a constellation having 2^(m+n) constellation points and a corresponding mapping of the 2^(m+n) constellation points thereby generating a sequence of discrete valued modulation symbols;

convolutional interleaving the sequence of discrete valued modulation symbols using a second convolutional interleave thereby generating a scrambled sequence of discrete valued modulation symbols;

transforming the scrambled sequence of discrete valued modulation symbols into a continuous time transmit signal that comports with a communication channel; and

launching the continuous time transmit signal into the communication channel.

19. The method of claim 18, wherein:

a first bit of the RS coded bit stream is provided to the first RS coded bit stream;

a second bit of the RS coded bit stream is provided to the second RS coded bit stream;

a third bit of the RS coded bit stream is provided to the first RS coded bit stream; and

a fourth bit of the RS coded bit stream is provided to the second RS coded bit stream.

20. The method of claim 18, wherein:

a first plurality of bits of the RS coded bit stream is provided to the first RS coded bit stream;

a second plurality of bits of the RS coded bit stream is provided to the second RS coded bit stream;

a third plurality of bits of the RS coded bit stream is provided to the first RS coded bit stream; and

a fourth plurality of bits of the RS coded bit stream is provided to the second RS coded bit stream.