Bi-directional transistor and method therefor

• US 20060226439A1
• Filed: 03/31/2005
• Published: 10/12/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Robb, Stephen P., Robb, Francine Y., Hightower, Robert F.
• Granted Patent: US 7,297,603 B2
• Time in Patent Office: Days
• US Class Current: 257/119
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

In one embodiment, a transistor is formed to conduct current in both directions through the transistor.

Claims

1. A bi-directional transistor comprising:

a first MOS transistor having a body region, a first current carrying electrode, and a second current carrying electrode; and

a switch configured to selectively couple the body region of the first MOS transistor to the first current carrying electrode or the second current carrying electrode of the first MOS transistor responsively to signals applied to the source and the drain of the first MOS transistor.

2. The bi-directional transistor of claim 1 wherein the first MOS transistor is a vertical MOS power transistor.

3. The bi-directional transistor of claim 1 wherein the switch configured to selectively couple the body region of the first MOS transistor to the first current carrying electrode or the second current carrying electrode of the first MOS transistor responsively to signals applied to the first current carrying electrode and the second current carrying electrode of the first MOS transistor includes a first switch transistor having a first current carrying electrode coupled to the body region, a second current carrying electrode coupled to the drain of the first MOS transistor, and a control electrode coupled to the source of the first MOS transistor.

4. The bi-directional transistor of claim 3 further including a second switch transistor having a first current carrying electrode coupled to the body region, a second current carrying electrode coupled to the first current carrying electrode of the first MOS transistor, and a control electrode coupled to the second current carrying electrode of the first MOS transistor.

5. The bi-directional transistor of claim 1 wherein the body region of the first MOS transistor is devoid of a direct electrical connection to the first current carrying electrode of the first MOS transistor.

6. The bi-directional transistor of claim 1 wherein the switch configured to selectively couple the body region of the first MOS transistor to the first current carrying electrode or the second current carrying electrode of the first MOS transistor includes a second MOS transistor and a third MOS transistor configured to selectively couple the body region to the first current carrying electrode or the second current carrying electrode of the first MOS transistor.

7. The bi-directional transistor of claim 6 wherein the second MOS transistor and the third MOS transistor are lateral MOS transistors.

8. The bi-directional transistor of claim 6 wherein the second MOS transistor is a lateral MOS transistor and the third MOS transistor is a vertical MOS transistor.

9. The bi-directional transistor of claim 1 wherein the first MOS transistor is a vertical MOS trench gate transistor.

10. A method of forming a bi-directional transistor comprising:

forming a first MOS transistor on a semiconductor substrate of a first conductivity type;

forming a body region of the first MOS transistor on a surface of the semiconductor substrate and isolated from a first current carrying electrode region of the first MOS transistor by a first P-N junction and isolated from a second current carrying electrode region of the first MOS transistor by a second P-N junction; and

forming a second MOS transistor coupled to selectively couple the body region of the first MOS transistor to the first current carrying electrode of the first MOS transistor.

11. The method of claim 10 further including forming the second MOS transistor electrically coupled between the body region of the first MOS transistor and the second current carrying electrode region of the first MOS transistor.

12. The method of claim 10 wherein the first MOS transistor is a vertical transistor and the second MOS transistor is a lateral MOS transistor formed on the semiconductor substrate.

13. The method of claim 10 wherein the first MOS transistor is a vertical transistor and the second MOS transistor is a vertical MOS transistor formed on the semiconductor substrate.

14. The method of claim 10 further including a third MOS transistor coupled to selectively couple the body region of the first MOS transistor to a second current carrying electrode of the first MOS transistor.

15. A method of forming a bi-directional transistor comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first doped region of a second conductivity type on a surface of the semiconductor substrate as a body region of a first transistor;

forming a second doped region of the first conductivity type within the first doped region and extending a first distance into the first doped region as a first current carrying electrode region of the first transistor; and

forming a third doped region of the first conductivity type extending from the second doped region a second distance into the first doped region.

16. The method of claim 15 further including forming a fourth doped region of the second conductivity type on the surface of the semiconductor substrate and spaced apart from the first doped region;

forming a source and a drain of a second transistor in the fourth doped region; and

coupling the second transistor electrically between the first doped region and the semiconductor substrate.

17. The method of claim 16 wherein forming the source and the drain of the second transistor in the fourth doped region includes forming a fifth doped region within the fourth doped region;

forming a sixth doped region within the fourth doped region and spaced apart from the fifth doped region;

electrically coupling the fifth doped region to the first doped region; and

coupling the sixth doped region to the semiconductor substrate.

18. The method of claim 15 further including forming a fourth doped region of the second conductivity type on the surface of the semiconductor substrate and spaced apart from the first doped region;

forming a source and a drain of a second transistor in the fourth doped region; and

coupling the second transistor electrically between the first doped region and the second doped region.

19. The method of claim 18 wherein forming the source and the drain of the second transistor in the fourth doped region includes forming a fifth doped region within the fourth doped region;

forming a sixth doped region within the fourth doped region and spaced apart from the fifth doped region;

electrically coupling the fifth doped region to the first doped region; and

coupling the sixth doped region to the second doped region.

20. The method of claim 15 wherein forming the first doped region of the second conductivity type on the surface of the semiconductor substrate as the body region of the first transistor includes forming the first transistor as a vertical transistor.