Semiconductor device having a lateral channel and contacts on opposing surfaces thereof
First Claim
1. A semiconductor device, comprising:
- a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof;
a lateral channel above said conductive substrate;
a second contact above said lateral channel; and
an interconnect that connects said lateral channel to said conductive substrate operable to provide a low resistance coupling between said first contact and said lateral channel.
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Accused Products
Abstract
A semiconductor device having a lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel.
146 Citations
60 Claims
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1. A semiconductor device, comprising:
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a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof;
a lateral channel above said conductive substrate;
a second contact above said lateral channel; and
an interconnect that connects said lateral channel to said conductive substrate operable to provide a low resistance coupling between said first contact and said lateral channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A semiconductor device, comprising:
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a substrate having a source contact covering a substantial portion of a bottom surface thereof;
a first buffer layer formed over said substrate;
an isolation layer formed over said first buffer layer;
a first spacer layer formed over said isolation layer;
a second buffer layer formed over said first spacer layer;
a first barrier layer formed over said second buffer layer;
a second spacer layer formed over said first barrier layer;
a lateral channel formed over said second spacer layer;
a third spacer layer formed over said lateral channel;
a second barrier layer formed over said third spacer layer;
a recess layer formed over said second barrier layer;
an etch-stop layer formed over said recess layer;
first and second source/drain contact layers formed over said etch-stop layer;
a source interconnect that connects said lateral channel to said substrate operable to provide a low resistance coupling between said source contact and said lateral channel;
a gate located in a gate recess formed though said first and second source/drain contact layers, said etch-stop and said recess layer;
a dielectric layer formed over said gate, and said first and second source/drain contact layers;
a drain post located in a drain via formed through said dielectric layer and over said first second source/drain contact layers; and
a drain contact coupled to said drain post. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A semiconductor device, comprising:
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a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof;
a lateral channel above said conductive substrate;
a second contact above said lateral channel;
an interconnect that connects said lateral channel to said conductive substrate operable to provide a low resistance coupling between said first contact and said lateral channel; and
an intrinsic body diode operable to provide a conductive path between said first and second contacts. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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Specification